HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 266

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
In phase counting mode, selections for external clock edge made with the CKEG1 and CKEG0
bits in timer control register 2 (TCR2) and the counter clock selection made in the TPSC2–TPSC0
bits are ignored. The phase counting mode described above takes priority. Settings for counter
clear conditions in the CCLR1 and CCLR0 bits in TCR2 and settings for timer I/O control register
2 (TIOR2), timer interrupt enable register (TIER2), and timer status register 2 (TSR2) compare
match/input capture functions and interrupts, however, are valid even in phase counting mode.
Bit 5—Flag Direction (FDIR): FDIR selects the setting condition for the overflow flag (OVF) in
timer status register 2 (TSR2). This bit is valid no matter which mode channel 2 is operating in.
Bit 5: FDIR
0
1
Bit 4—PWM Mode 4 (PWM4): PWM4 selects PWM mode for channel 4. When the PWM4 bit
is set to 1 and PWM mode is entered, the TIOCA4 pin becomes a PWM output pin. 1 is output on
a compare match of general register A4 (GRA4); 0 is output on a compare match of general
register B4 (GRB4). When complementary PWM mode or reset-synchronized PWM mode is set
by the CMD1 and CMD0 bits in the timer function control register (TFCR), the setting of this bit
is ignored in favor of the settings of CMD1 and CMD0.
Bit 4: PWM4
0
1
Bit 3—PWM Mode 3 (PWM3): PWM3 selects the PWM mode for channel 3. When the PWM3
bit is set to 1 and PWM mode is entered, the TIOCA3 pin becomes a PWM output pin. 1 is output
on a compare match of general register A3 (GRA3); 0 is output on a compare match of general
register B3 (GRB3). When complementary PWM mode or reset-synchronized PWM mode is set
by the CMD1 and CMD0 bits in the timer function control register (TFCR), the setting of this bit
is ignored in favor of the settings of CMD1 and CMD0.
Bit 3: PWM3
0
1
Bit 2—PWM Mode 2 (PWM2): PWM2 selects the PWM mode for channel 2. When the PWM2
bit is set to 1 and PWM mode is entered, the TIOCA2 pin becomes a PWM output pin. 1 is output
Rev. 7.00 Jan 31, 2006 page 238 of 658
REJ09B0272-0700
Description
OVF of TSR2 is set to 1 when TCNT2 overflows or underflows
OVF of TSR2 is set to 1 when TCNT2 overflows
Description
Channel 4 operates normally
Channel 4 operates in PWM mode
Description
Channel 3 operates normally
Channel 3 operates in PWM mode
(Initial value)
(Initial value)
(Initial value)