HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 285

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Buffer Mode:
10.4.2
Counter Operation: When a start bit (STR0–STR4) in the timer start register (TSTR) is set to 1,
the corresponding timer counter (TCNT) starts counting. There are two counting modes: a free-
running mode and a periodic mode.
When GR is an output compare register: The BR value of each channel is transferred to GR
when a compare match occurs.
When GR is an input capture register: The TCNT value is transferred to GR when an input
capture occurs and simultaneously the value previously stored in GR is transferred to BR.
Complementary PWM mode: When TCNT3 and TCNT4 change count directions, the BR
value is transferred to GR.
Reset-synchronized PWM mode: The BR value is transferred to GR upon a GRA3 compare
match.
Procedure for selecting counting mode (figure 10.14):
1. Set bits TPSC2–TPSC0 in TCR to select the counter clock source. If an external clock
2. To operate as a periodic counter, set CCLR1 and CCLR0 in TCR to select whether to clear
3. Set GRA or GRB selected in step 2 as an output compare register using the timer I/O
4. Write the desired cycle value in GRA or GRB selected in step 1.
5.
source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge of the
external clock signal.
TCNT at GRA compare match or GRB compare match.
control register (TIOR).
Set the STR bit in TSTR to 1 to start counting.
Basic Functions
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Rev. 7.00 Jan 31, 2006 page 257 of 658
REJ09B0272-0700

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