HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 223

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

converter (table 9.4). When this mode is selected, if DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, NMIF = 0, AE = 0), a transfer is performed upon input of a transfer request signal. The
source of the transfer request does not have to be the data transfer source or destination. When
RXI is set as the transfer request, however, the transfer source must be the SCI’s receive data
register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the
SCI’s transmit data register (TDR). If the transfer request is from the A/D converter, the data
transfer source must be an A/D converter register.
Table 9.4
RS
3
0
0
0
0
1
1
1
1
1
SCI0, SCI1: Serial communication interface channels 0 and 1
ITU0-ITU3: Channels 0–3 of the 16-bit integrated timer pulse unit
RDR0, RDR1: Receive data registers 0, 1 of SCI
TDR0, TDR1: Transmit data registers 0, 1 of SCI
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip memory, on-chip supporting
RS
2
1
1
1
1
0
0
0
0
1
module (excluding DMAC)
RS
1
0
0
1
1
0
0
1
1
0
Selecting On-Chip Peripheral Module Request Modes with the RS Bits
RS
0
0
1
0
1
0
1
0
1
1
DMA
Transfer
Request
Source
SCI0
receiver
SCI0
transmitter
SCI1
receiver
SCI1
transmitter
ITU0
ITU1
ITU2
ITU3
A/D
converter
DMA Transfer Request
Signal
RXI0 (SCI0 receive data full
interrupt transfer request)
TXI0 (SCI0 transmit data
empty interrupt transfer
request)
RXI1 (SCI1 receive data full
interrupt transfer request)
TXI1 (SCI1 transmit data
empty interrupt transfer
request)
IMIA0 (ITU0 input capture A/
compare match A)
IMIA1 (ITU1 input capture A/
compare match A)
IMIA2 (ITU2 input capture A/
compare match A)
IMIA3 (ITU3 input capture A/
compare match A)
ADI (A/D conversion end
interrupt)
Section 9 Direct Memory Access Controller (DMAC)
Rev. 7.00 Jan 31, 2006 page 195 of 658
Source
RDR0
Any
RDR1
Any *
Any *
Any *
Any *
Any *
ADDR
TDR0
Any
Desti-
nation Bus Mode
Any *
Any *
TDR1
Any *
Any *
Any *
Any *
REJ09B0272-0700
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