HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 226
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
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Section 9 Direct Memory Access Controller (DMAC)
1. Transfer requests are generated simultaneously for channels 1 and 0.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 1 waits for
3. A channel 3 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 becomes the lowest priority.
5. At this point, channel 3 has a higher priority than channel 1, so the channel 3 transfer begins
6. When the channel 3 transfer ends, channel 3 becomes the lowest priority.
7. The channel 1 transfer begins.
8.
Rev. 7.00 Jan 31, 2006 page 198 of 658
REJ09B0272-0700
transfer).
waiting)
(channel 1 waits for transfer).
When the channel 1 transfer ends, channels 1 and 2 shift downward in priority so that channel
1 becomes the lowest priority.
(1) Channels 0 and 1
Transfer request
(3) Channel 3
Figure 9.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s)
1
1, 3
1
None
(2) Channel 0
(4) Channel 0
(5) Channel 3
(6) Channel 3
(7) Channel 1
(8) Channel 1
DMAC operation
transfer starts
transfer ends
transfer starts
transfer ends
transfer starts
transfer ends
Priority order
Priority order
Priority order
changes
changes
changes
Channel priority
0
3
2
0
3
2
1
3
2
1
0
2
1
0
3
1
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