HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 448

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 A/D Converter
14.4
The A/D converter operates by successive approximations with a 10-bit resolution. Its two modes,
single mode and scan mode, are described below.
14.4.1
In single mode, A/D conversion is performed on a single channel. A/D conversion starts when the
ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or an external trigger
input. During the conversion process the ADST bit remains set at 1. When the conversion is
completed, the ADST bit is automatically cleared to 0.
When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) in
ADCSR is also set to 1, an A/D conversion interrupt (ADI) is requested. When ADCSR is read
and 1 is written in the ADF bit, the ADF bit is cleared to 0.
Before changing a mode or analog input channel, clear the ADST bit in ADCSR to 0 to stop A/D
conversion in order to prevent malfunctions. Setting the ADST bit to 1 after changing the mode or
channel starts A/D conversion again (changing the mode or channel and setting the ADST bit can
be performed simultaneously).
The following is an example of the A/D conversion process in single mode when channel 1 (AN1)
is selected. See figure 14.3 for the timing.
1. The program selects single mode (SCAN = 0) and input channel AN1 (CH2 = CH1 = 0, CH0 =
2. At the end of the conversion process the A/D converter transfers the result to register ADDRB,
3. Since ADF = 1 and ADIE = 1, an A/D interrupt is requested.
4. The A/D interrupt handling routine is started.
5. The interrupt handling routine reads the ADF value; since it is 1, it writes a 0 into the ADF bit.
6. The interrupt handling routine reads and processes the A/D conversion result (ADDRB).
7.
Steps 2–7 can now be repeated by setting the ADST bit to 1 again.
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1), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to 1 to start A/D
conversion.
sets the ADF bit to 1, clears the ADST bit to 0, and halts.
The routine ends.
Operation
Single Mode (SCAN = 0)