HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 186

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
8.5.6
The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit
(RMODE) in the refresh control register (RCR), either CAS-before-RAS refresh (CBR) or self-
refresh can be selected. When no refresh is performed, the refresh timer counter (RTCNT) can be
used as an 8-bit interval timer.
CAS-Before-RAS Refresh (CBR): A refresh is performed at an interval determined by the input
clock selected with clock select bits 2–0 (CKS2–CKS0) in the refresh timer control/status register
(RTCSR) and the value set in the refresh time constant register (RTCOR). Set the values of
RTCOR and CKS2–CKS0 so they satisfy the refresh interval specifications of the DRAM being
used.
To perform a CBR refresh, clear the RMODE bit in RCR to 0 and then set the refresh control bit
(RFSHE) bit to 1. Also write the required values to RTCNT and RTCOR. When the clock is
subsequently selected with the CKS2–CKS0 bits in RTCSR, RTCNT will begin to increment from
its current value. The RTCNT value is constantly compared with the RTCOR value and a CBR
Rev. 7.00 Jan 31, 2006 page 158 of 658
REJ09B0272-0700
AD15–
A21–
RAS up mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a
DRAM access pauses for access to another space. Burst operation continues only while
DRAM access is continuous. Figure 8.28 shows the timing when an external memory space
access occurs during burst operation in RAS up mode.
RAS
CAS
AD0
CK
A0
Refresh Control
T
p
Row address
T
r
DRAM access
address 1
Column
Figure 8.28 RAS Up Mode
T
c
Data 1
address 2
Column
T
c
External memory
Data 2
space access
External memory
memory data
T1
External
address
T
p
DRAM access
Row address
T
r
address 3
Column
T
c
Data 3