HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 233

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TM bits in
CHCR0–CHCR3.
Figure 9.10 Transfer Example in Cycle-Steal Mode (Dual Address Mode, DREQ
Figure 9.9 DMA Transfer Timing in Dual Address Mode (External Memory Space to
Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (word or
byte) DMA transfer. When another transfer request occurs, the bus is obtained from the other
bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus is
passed to the other bus master. This is repeated until the transfer end conditions are satisfied.
Cycle-steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 9.10 shows an example of DMA transfer timing in cycle-steal mode.
Transfer conditions shown in the figure are:
Bus cycle
Dual address mode
DREQ level detection
DREQ
External Memory Space Transfer with DACK Output in Read Cycle)
D15–D0
CPU
A21–A0
DACK
WRH
WRL
CSn
RD
CK
CPU
CPU
Source address
DMAC DMAC
Read
Detection)
Section 9 Direct Memory Access Controller (DMAC)
Write
Bus returned to CPU
Rev. 7.00 Jan 31, 2006 page 205 of 658
Destination address
CPU
DMAC DMAC
Read
Write
REJ09B0272-0700
DREQ
DREQ Level
DREQ
CPU