HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 133

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.1.3
Table 8.1 shows the BSC pin configuration.
Table 8.1
Name
Chip select 7–0
Read
High write
Low write
Write
High byte strobe
Low byte strobe
Row address strobe RAS
High column
address strobe
Low column
address strobe
Address hold
Wait
Address bus
Data bus
Data bus parity high DPH
Data bus parity low
Notes: 1. Doubles with the WRL pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus
2. Doubles with the A0 pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus
3. Doubles with the WRH pin. (Selected by the BAS bit in BCR. See section 8.2.1, Bus
Pin Configuration
Control Register (BCR), for details.)
Control Register (BCR), for details.)
Control Register (BCR), for details.)
Pin Configuration
Abbreviation
CS7–CS0
RD
WRH
WRL
WR *
HBS *
LBS *
CASH
CASL
AH
WAIT
A21–A0
AD15–AD0
DPL
1
3
2
I/O
O
O
O
O
O
O
O
O
O
O
O
I
O
I/O
I/O
I/O
Function
Chip select signal that indicates the area being
accessed
Strobe signal that indicates the read cycle
Strobe signal that indicates write cycle to upper 8
bits
Strobe signal that indicates write cycle to lower 8
bits
Strobe signal that indicates write cycle
Strobe signal that indicates access to upper 8 bits
Strobe signal that indicates access to lower 8 bits
DRAM row address strobe signal
Column address strobe signal for accessing the
upper 8 bits of the DRAM
Column address strobe signal for accessing the
lower 8 bits of the DRAM
Signal for holding the address for address/data
multiplexing
Wait state request signal
Address output
Data I/O. During address/data multiplexing,
address output and data input/output
Parity data I/O for upper byte
Parity data I/O for lower byte
Rev. 7.00 Jan 31, 2006 page 105 of 658
Section 8 Bus State Controller (BSC)
REJ09B0272-0700