HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 231

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Dual Address Mode
In dual address mode, both the transfer source and destination are accessed (selectable) by an
address. The source and destination can be located externally or internally. The source is
accessed in the read cycle and the destination in the write cycle, so the transfer is performed in
two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8
shows an example of a transfer between two external memories in which data is read from one
memory in the read cycle and written to the other memory in the following write cycle.
D15–D0
A21–A0
DACK
D15–D0
A21–A0
CSn
DACK
RD
WRH
CK
WRL
CSn
Figure 9.7 Examples of DMA Transfer Timing in Single Address Mode
CK
(a) External device with DACK to external memory space
(b) External memory space to external device with DACK
Section 9 Direct Memory Access Controller (DMAC)
Address output to external memory space
Data output from external memory space
RD signal to external memory space
DACK signal to external device with DACK
(active-low)
Address output to external memory space
Data output from external device with DACK
DACK signal to external device with DACK
(active-low)
WR signal to external memory space
Rev. 7.00 Jan 31, 2006 page 203 of 658
REJ09B0272-0700

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