HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 356

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Programmable Timing Pattern Controller (TPC)
11.3.3
Settings for Ordinary TPC Output (Figure 11.4):
1. Select GRA as the output compare register (output disable) with the timer I/O control register
2. Set the TPC output trigger cycle.
3. Select the counter clock with the TPSC2–TPSC0 bits in the timer control register (TCR).
4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to NDR can
5. Set the initial output value in the I/O port data register to be used by the TPC.
6. Set the I/O port control register to be used by the TPC as the TP pin function (11).
7. Set to 1 the bit that performs TPC output to the next data enable register (NDER).
8. Select the ITU compare match that will be the TPC output trigger using the TPC output control
9. Set the next TPC output value in NDR.
10. Set 1 in the STR bit of the timer start register (TSTR) and start the timer counter.
11. Set the next output value in NDR whenever an IMIA interrupt is generated.
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REJ09B0272-0700
(TIOR).
Select the counter clear sources with the CCLR1 and CCLR0 bits.
also be set using the DMAC.
register (TPCR).
TP15–TP8
Compare
match A
NDRB
PBDR
TCNT
signal
GRA
Examples of Use of Ordinary TPC Output
CK
Figure 11.3 Transfer and Output Timing for NDRB Data (Example)
m
m
N
N
n
N + 1
n
n