HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 249

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Notes on use of the SLEEP instruction
7. Sampling of DREQ
a. Operation contents
b. Remedy
In cases when the CPU is not carrying out any other processing but is waiting for the DMAC
to end its transfer during DMAC operation, do not use the SLEEP instruction, but use the
transfer end flag bit (TE) in the channel DMA control register and a polling software loop.
If DREQ is set to level detection in DMA cycle-steal mode, sampling of DREQ may take place
before DACK is output. Note that some system configurations involve unnecessary DMA
transfers.
Operation:
As shown in Figure 9.25, sampling of DREQ is carried out immediately before the rising edge
of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus cycle
where DACK is output.
If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be
carried out before DACK is output.
When a DMAC bus cycle is entered immediately after executing a SLEEP instruction,
there are cases when DMA transfer is not carried out correctly.
Stop operation (for example, by clearing the DMA enable bit (DE) in the DMA channel
control register (CHCRn)) before entering sleep mode.
To use the DMAC when in sleep mode, first exit sleep mode by means of an interrupt.
Number of states of
: DMAC bus cycle
DMAC bus cycle
Figure 9.25 DREQ
1
2
3
4
DREQ
DREQ Sampling Points
DREQ
Section 9 Direct Memory Access Controller (DMAC)
Sampling point
Rev. 7.00 Jan 31, 2006 page 221 of 658
REJ09B0272-0700