HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 271

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.2.7
Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers.
Each GR is a 16-bit read/write register that can function as either an output compare register or an
input capture register. The function is selected by settings in the timer I/O control register (TIOR).
When a general register (GRA/GRB) is used as an output compare register, its value is constantly
compared with the timer counter (TCNT) value. When the two values match (compare match), the
IMFA/IMFB bit is set to 1 in the timer status register (TSR). If compare match output is selected
in TIOR, a specified value is output at the output compare pin.
When a general register is used as an input capture register, an external input capture signal is
detected and the TCNT value is stored. The IMFA/IMFB bit in the corresponding TSR is set to 1
at the same time. The valid edge or edges of the input capture signal are selected in TIOR. The
TIOR setting is ignored when set for PWM mode, complementary PWM mode, or reset-
synchronized PWM mode.
General registers are connected to the CPU by a 16-bit bus, so general registers can be written or
read by either word access or byte access. General registers are initialized as output compare
registers (no pin output) by a reset and in standby mode. The initial value is H'FFFF.
Table 10.5 General Registers A and B (GRA and GRB)
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Channel Abbreviation Function
0
1
2
3
4
General Registers A and B (GRA and GRB)
GRA0, GRB0 Output compare/input capture dual register
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3 Output compare/input capture dual register. Can also be set for buffer
GRA4, GRB4 operation in combination with the buffer registers (BRA, BRB)
R/W
R/W
15
1
7
1
R/W
R/W
14
1
6
1
R/W
R/W
13
1
5
1
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
R/W
R/W
12
1
4
1
Rev. 7.00 Jan 31, 2006 page 243 of 658
R/W
R/W
11
1
3
1
R/W
R/W
10
1
2
1
REJ09B0272-0700
R/W
R/W
9
1
1
1
R/W
R/W
8
1
0
1