HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 284
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
- Current page: 284 of 689
- Download datasheet (5Mb)
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.4
10.4.1
The operation modes are described below.
Ordinary Operation: Each channel has a timer counter (TCNT) and general register (GR). The
TCNT is an up-counter and can also operate as a free-running counter, periodic counter, or
external event counter. General registers A and B (GRA and GRB) can be used as output compare
registers or input capture registers.
Synchronized Operation: The TCNT of a channel set for synchronized operation perform
synchronized presetting. When any TCNT of a channel operating in the synchronized mode is
rewritten, the TCNTs in other channels are simultaneously rewritten as well. The CCLR1 and
CCLR0 bits of the timer control register of multiple channels set for synchronous operation can be
set to clear the TCNTs simultaneously.
PWM Mode: In PWM mode, a PWM waveform is output from the TIOCA pin. Output becomes
1 upon compare match A and 0 upon compare match B. GRA and GRB can be set so that the
PWM waveform output has a duty cycle between 0% and 100%. When set for PWM mode, the
GRA and GRB automatically become output compare registers.
Reset-Synchronized PWM Mode: Three pairs of positive and negative PWM waveforms can be
obtained using channels 3 and 4 (the three phases of the PWM waveform share a transition point
on one side). When set for reset-synchronized PWM mode, GRA3, GRB3, GRA4, and GRB4
automatically become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4,
TIOCB4, and TOCXB4 pins also become PWM output pins and TCNT3 becomes an up-counter.
TCNT4 functions independently (although GRA and GRB are isolated from TCNT4).
Complementary PWM Mode: Three pairs of complementary positive and negative PWM
waveforms whose positive and negative phases do not overlap can be obtained using channels 3
and 4. When set for complementary PWM mode, GRA3, GRB3, GRA4, and GRB4 automatically
become output compare registers. The TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and
TOCXB4 pins also become PWM output pins while TCNT3 and TCNT4 become up-counters.
Phase Counting Mode: In phase counting mode, the phase differential between two clocks input
from the TCLKA and TCLKB pins is detected and the TCNT2 operates as an up/down-counter. In
phase counting mode, the TCLKA and TCLKB pins become clock inputs and TCNT2 functions as
an up/down-counter.
Rev. 7.00 Jan 31, 2006 page 256 of 658
REJ09B0272-0700
Operation
Overview
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