HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 314

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Figure 10.50 shows an example of input capture operation in buffer mode between GRA and BRA
with GRA as an input capture register. TCNT is cleared by input capture B. The falling edge is
selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at
TIOCA. When the TCNT value is stored in GRA by input capture A, the previous GRA value is
transferred to BRA. The timing is shown in figure 10.51.
Rev. 7.00 Jan 31, 2006 page 286 of 658
REJ09B0272-0700
H' 0250
H' 0200
H' 0100
H' 0000
transfer signal
TIOCB
TIOCA
TCNT value
Figure 10.48 Buffer Mode Operation Example 1 (Output Compare Register)
match signal
GRB
GRA
BRA
Compare
Figure 10.49 Compare Match Timing Example for Buffer Operation
Buffer
TCNT
GR
CK
BR
H' 0250
H' 0200
n
n
H' 0200
H' 0100
Counter cleared by compare match B
Compare match A
H' 0100
N
n + 1
N
H' 0200
H' 0200
Time
Toggle
output
Toggle
output

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