AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 713

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6209F–ATARM–17-Feb-09
Version
6209D
Comments
AT91SAM7XC512 added to product family.
TFBGA package to
Characteristics”
Peripheral and System Controller Memory Maps consolidated in
Internal Memory Area 3 is “Internal ROM”
IP Block Evolution:
RSTC:Section 13.3 ”Functional Description”
oscillator.
RTT:
to end of section.
WDT:
86
EFC:
AT91SAM7XC512 with multiple EFCs.
SAM Boot:
Section 21.4 “SAM-BA Boot” on page 135
Figure 21-1, ”Boot Program Algorithm Flow Diagram” on page 135
PDC: Corrected description of user interface in
Corrected bit name to ENDTX in
AIC:
AIC_SVR register changed to AIC_SMR register.
Section 23.8 “Advanced Interrupt Controller (AIC) User Interface” on page 166, Table 23-2:
note
Naming convention for AIC_FVR register harmonized in
Register” on page 169
PMC:
of Master Clock and Processor Clock”
Corrected name of bitfield PRES in
Removed reference to PMC_ACKR register in
Updated OUTx bit descriptions in
Added note defining PIDx in
Section 25.9.5 “PMC Peripheral Clock Disable Register” on page 194
Peripheral Clock Status Register” on page
Changed
DBGU: Corrected references from ice_nreset to Power-on Reset in
Functional Block Diagram, and in FNTRST bit description in
NTRST Register” on page
PIO:
Section 27.5.1 “Pull-up Resistor Control” on page 233
Figure 27-3, ”I/O Line Control Logic” on page 232
6th and 7th paragraph changed.
Section 23.7.3.1 “Priority Controller” on page 158:
(2)
Section 27.5.4 “Output Control” on page
Section 14.3 ”Functional
Section 19. ”Embedded Flash Controller (EFC)”
“Block Diagram” on page 85
Section 25.7 “Programming Sequence” on page 183
in reference to PID2...PID31 bit fields.
Section 24.2 “Slow Clock RC Oscillator” on page
Section 21.5 “Hardware and Software Constraints” on page 139
and
Section 4.
Section 42. ”AT91SAM7XC Ordering
and
228.
Section 23.7.4.5 “Fast Forcing” on page
Section 25.9.4 “PMC Peripheral Clock Enable Register” on page
”Package”,
Description”: Note (asynchronization between SCLK and MCK) added
Section 22.3.3 “Transfer Counters” on page
Section 25.9.9 “PMC Clock Generator PLL Register” on page
replaced. (WV changed to WDV)
Section 25.9.10 “PMC Master Clock Register” on page
AT91SAM7XC512/256/128 Preliminary
and to code.
Section 41. ”AT91SAM7XC512/256/128 Mechanical
Figure 18-3 on page 95
SAM-BA boot principle changed.
195.
“Features” on page
added information on startup counter for crystal
233, typo corrected.
Table 25-2, “Register Mapping,” on page
Section 22.1 “Overview” on page
change to I/O Line Control Logic
updated to reflect EFC configuration for
reference to resistor value removed
incorrect reference of SRCTYPE field to
Table
Information”.
change to
177.
Section 26.5.12 “Debug Unit Force
23-2,
1,
Figure 8-1 on page 18
“Description” on page 3
flow diagram replaced
Figure 26-1 on page
162.
“Functional Description” on page
Section 23.8.6 “AIC FIQ Vector
Step 4. on page
and
Section 25.9.6 “PMC
updated
142.
141.
184,
190.
206,
Global and
“Selection
199.
Added
194,
198.
Change
Request
Ref.
#2724
3005
2522
3002
2356
3086
2285, 2618
3050
05-460
2512
2548
05-506
1603
1719
2467, 2913
2468
1558
2832
05-346
05-497
3053
713