AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 508

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.3.1
36.3.2
36.3.2.1
508
AT91SAM7XC512/256/128 Preliminary
Operation Modes
Start Modes
Manual Mode
The AES supports the following modes of operation:
The data pre-processing, post-processing and data chaining for the concerned modes are auto-
matically performed. Refer to the NIST Special Publication 800-38A Recommendation for more
complete information.
These modes are selected by setting the OPMOD field in the AES Mode Register (AES_MR).
In CFB mode, five data sizes are possible (8 bits, 16 bits, 32 bits, 64 bits or 128 bits), config-
urable by means of the CFBS field in the mode register.
516.).
The SMOD field in the AES Mode Register (AES_MR) allows selection of the encryption (or
decryption) start mode.
The sequence is as follows:
Note:
Table 36-1.
• ECB: Electronic Code Book
• CBC: Cipher Block Chaining
• OFB: Output Feedback
• CFB: Cipher Feedback
• CTR: Counter
• Write the 128-bit/192-bit/256-bit key in the Key Registers (AES_KEYWxR).
• Write the initialization vector (or counter) in the Initialization Vector Registers (AES_IVxR).
• Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER),
• Write the data to be encrypted/decrypted in the authorized Input Data Registers (See
depending on whether an interrupt is required or not at the end of processing.
36-1).
Operation Mode
– CFB8 (CFB where the length of the data segment is 8 bits)
– CFB16 (CFB where the length of the data segment is 16 bits)
– CFB32 (CFB where the length of the data segment is 32 bits)
– CFB64 (CFB where the length of the data segment is 64 bits)
– CFB128 (CFB where the length of the data segment is 128 bits)
128-bit CFB
The Initialization Vector Registers concern all modes except ECB.
64-bit CFB
32-bit CFB
ECB
CBC
OFB
Authorized Input Data Registers
AES_IDATA1R and AES_IDATA2R
Input Data Registers to Write
AES_IDATA1R
(See “AES Mode Register” on page
All
All
All
All
6209F–ATARM–17-Feb-09
Table