AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 148

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 21-1.
21.2.2
148
Signal Name
VDDFLASH
VDDIO
VDDCORE
VDDPLL
GND
XIN
TST
PGMEN0
PGMEN1
PGMNCMD
PGMRDY
PGMNOE
PGMNVALID
PGMM[3:0]
PGMD[15:0]
AT91SAM7XC512/256/128 Preliminary
Signal Names
Signal Description List
Function
Flash Power Supply
I/O Lines Power Supply
Core Power Supply
PLL Power Supply
Ground
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Test Mode Select
Test Mode Select
Test Mode Select
Valid command available
0: Device is busy
1: Device is ready for a new command
Output Enable (active high)
0: DATA[15:0] is in input mode
1: DATA[15:0] is in output mode
Specifies DATA type (See
Bi-directional data bus
Depending on the MODE settings, DATA is latched in different internal registers.
Table 21-2.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored
in the command register.
MODE[3:0]
0000
0001
0010
0101
Default
Mode Coding
Table 21-2
Symbol
CMDE
ADDR0
ADDR1
DATA
IDLE
Clocks
Power
)
Test
PIO
Input/Output
Ground
Output
Output
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Data
Command Register
Address Register LSBs
Data Register
No register
Active
Level
High
High
High
High
Low
Low
Low
Comments
32KHz to 50MHz
Must be connected to VDDIO
Must be connected to VDDIO
Must be connected to VDDIO
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
6209F–ATARM–17-Feb-09