AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 512

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 36-3.
Note:
Warning: In PDC mode, reading to the Output Data registers before the last data transfer may lead to unpredictable result.
36.3.4
36.3.4.1
512
DATRDY Flag Clearing
Encryption/Decryption
Encrypted/Decrypted
Data Result Location
Condition
1. Depending on the mode, there are other ways of clearing the DATRDY flag. See
End of
AT91SAM7XC512/256/128 Preliminary
Security Features
page 522
Countermeasures
Last Output Mode Behavior versus Start Modes
(1)
.
Figure 36-4. PDC Mode with LOD = 1
Table 36-3
The AES also features hardware countermeasures that can be useful to protect data against Dif-
ferential Power Analysis (DPA) attacks.
These countermeasures can be enabled through the CTYPE field in the AES Mode Register.
This field is write-only, and all changes to it are taken into account if, at the same time, the Coun-
termeasure Key (CKEY field) is correctly written (see
Note:
By default, all the countermeasures are enabled.
The best throughput is achieved with all the countermeasures disabled. On the other hand, the
best protection is achieved with all of them enabled.
The LOADSEED bit in the AES Control Register (AES_CR) restarts the countermeasures gen-
erator to an internal predefined value.
Data Register must be
At least one Output
In the Output Data
ENDTX (or TXBUFE)
Registers
LOD = 0
DATRDY
Enabling countermeasures has an impact on the AES encryption/decryption throughput.
read
summarizes the different cases.
Manual and Auto Modes
DATRDY
Enable PDC Channels (only Transmit Channels)
Register must be written
At least one Input Data
In the Output Data
Multiple Encryption or Decryption Processes
Registers
LOD = 1
DATRDY
ENDRX (or RXBUFF)
Register (AES_RPR)
Receive Pointer
specified in the
At the address
“AES Mode Register” on page
Not used
LOD = 0
“AES Interrupt Status Register” on
PDC Mode
Managed by the PDC
ENDTX (or TXBUFE)
In the Output Data
6209F–ATARM–17-Feb-09
then DATRDY
Registers
LOD = 1
516).