AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 564

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 38-9. Disabling Low-power Mode
38.7
38.7.1
6209F–ATARM–17-Feb-09
Functional Description
(CAN_MSRx)
CAN Controller Initialization
(CAN_SR)
WAKEUP
(CAN_MR)
(CAN_SR)
CAN BUS
SLEEP
MRDY
LPM
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated
by the Power Management Controller (PMC) and the CAN controller interrupt line must be
enabled by the interrupt controller (AIC).
The CAN controller must be initialized with the CAN network parameters. The CAN_BR register
defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller
is enabled by setting the CANEN field in the CAN_MR register.
The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage,
the internal CAN controller state machine is reset, error counters are reset to 0, error flags are
reset to 0.
Once the CAN controller is enabled, bus synchronization is done automatically by scanning
eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when
the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset).
The CAN controller can start listening to the network in Autobaud Mode. In this case, the error
counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags,
the CAN_BR register values synchronized with the network. Once no error has been detected,
the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register.
Message lost
AT91SAM7XC512/256/128 Preliminary
Interframe synchronization
Bus Activity Detected
Message x
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