AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 591

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38.8.8
Name:
Access Type:
• MTIMESTAMPx: Timestamp
This field represents the internal CAN controller 16-bit timer value.
If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field
at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in
the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in
the CAN_SR register. This flag is cleared by reading the CAN_SR register.
Note:
6209F–ATARM–17-Feb-09
MTIMESTAMP
MTIMESTAMP
31
23
15
15
–
–
7
7
The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR.
CAN Timestamp Register
MTIMESTAMP
MTIMESTAMP
30
22
14
14
CAN_TIMESTP
Read-only
–
–
6
6
MTIMESTAMP
MTIMESTAMP
29
21
13
13
–
–
5
5
MTIMESTAMP
MTIMESTAMP
AT91SAM7XC512/256/128 Preliminary
28
20
12
12
–
–
4
4
MTIMESTAMP
MTIMESTAMP
27
19
11
11
–
–
3
3
MTIMESTAMP
MTIMESTAMP
26
18
10
10
–
–
2
2
MTIMESTAMP
MTIMESTAMP
25
17
–
–
9
1
9
1
MTIMESTAMP
MTIMESTAMP
24
16
–
–
8
0
8
0
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