AT91SAM7XC512-CU Atmel, AT91SAM7XC512-CU Datasheet - Page 710

• Manufacturer Part Number: AT91SAM7XC512-CU
• Description: MCU ARM 512K HS FLASH 100-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7XC512-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: MII, SPI, TWI
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 62
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7X-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7XC-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7XC-EK - KIT EVAL FOR AT91SAM7XC256/128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

710
Version
6209E
(Continued) Comments
AT91SAM7XC512/256/128 Preliminary
AES,
Section 36.3.4.1 ”Countermeasures”
updated.
CAN,
Figure 38-7,”Line Error Mode”
versa have been inverted.
Section 38.6.4.6 ”Error Interrupt
Section 38.8.5 ”CAN Status
ERRA, ERRP.
Debug and Test,
Section 12.5.5 ”ID Code
Section 12.5.3 ”Debug
DBGU,
Section 27.1
Section 27.5.10 ”Debug Unit Chip ID
“SRAMSIZ: Internal SRAM Size” on page 254
Corrected bin values for 0x60 and 0xF0 and Architecture Identifier bit description for CAP7, AT91SAM7AQxx
Series and CAP11 in the bit description,
EMAC,
Section 39.5.3 ”Network Status
Section 39.3 ”Functional
FFPI,
Table
Global update to terms listed below:
Fuse → GPNVM
SFB → SGPB
CFB → CGPB
GFB → GGPB
Section 21.2.5.6 on page 154
explained.
MC,
Table 19-1, “Register Mapping,” on page
to AT91SAM7XC521
PIO,
Section 15.4.5 “Synchronous Data Output” on page
Section 15.6 “Parallel Input/Output Controller (PIO) User Interface” on page
PIO_PSR, PIO_ODSR, PIO_PDSR in Register Mapping table.
PMC,
Section 26.3 ”Processor Clock Controller”
Figure 25-2,”Typical Crystal Connection”
PWM,
Turned channel-dependent registers into indexed registers:
33.6.9 ”PWM Channel Mode
”PWM Channel Period
Channel Update Register”
Section 33.6.12 ”PWM Channel Counter
21-6,
Table 21-7
”Overview”, ...”two-pin UART can be used standalone for general purpose serial communication.
Register”,
Unit”, Debug Unit chip ID, typo corrected.
and
Register”, AT91SAM7XC512 product part number and JTAG ID code value updated.
Description”, Added information on clocks in first paragraph.
Table 21-15
Register”, added references to the new chapter in bit descriptions, WARN, BOFF,
Register”,
&
Conditions to switch from Error Active mode to Error Passive mode and vice
Register”, Corrected status for IDLE bit.
Handler”, added to datasheet.
Section 21.3.4.6 on page
Section 33.6.12 ”PWM Channel Counter
and
Register”, SRAM bit description added for AT91SAM7L in the bit field.
Section 33.6.10 ”PWM Channel Duty Cycle
“ARCH: Architecture Identifier” on page 255
updated.
Register”, typos corrected in bit description.
updated, removed C
126, updated table with line for EFC1, offset 0x70, with note specific
Section 36.4.1 ”AES Control Register”
....the processor clock can be disabled by writing.... PMC_SDR.
86, PIO_OWSR typo corrected.
161, security bit restraint on access to FFPI
Table 33-2, “Register
L1
and C
L2
labels.
Register”and
90, 10, footnotes updated on
LOADSEED description
Mapping”. See
Register”,
Section 33.6.13 ”PWM
Section 33.6.11
Section
6209F–ATARM–17-Feb-09
Change
Request
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