ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 74

• Manufacturer Part Number: ATMEGA16-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Modes of Operation
Normal Mode
Clear Timer on Compare
Match (CTC) Mode
74
ATmega16(L)
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and
Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM01:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output
should be set, cleared, or toggled at a compare match (See “Compare Match Output
Unit” on page 72.).
For detailed timing information refer to Figure 34, Figure 35, Figure 36 and Figure 37 in
“Timer/Counter Timing Diagrams” on page 79.
The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(
Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However,
combined with the timer overflow interrupt that automatically clears the
timer resolution can be increased by software. There are no special cases to consider in
the normal mode, a new counter value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using
the output compare to generate waveforms in Normal mode is not recommended, since
this will occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the
counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the
counter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 31. The counter value
(TCNT0) increases until a compare match occurs between TCNT0 and OCR0, and then
counter (TCNT0) is cleared.
Figure 31. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be
used for updating the TOP value. However, changing TOP to a value close to BOTTOM
TOV
TCNTn
OCn
(Toggle)
Period
0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The
1
2
3
4
OCn Interrupt Flag Set
TOV
2466J–AVR–10/04
(COMn1:0 = 1)
0 Flag, the
TOV
0