ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 110

• Manufacturer Part Number: ATMEGA16-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

110
ATmega16(L)
Table 45. Compare Output Mode, Fast PWM
Note:
Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Table 46. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
Note:
• Bit 3 – FOC1A: Force Output Compare for Channel A
• Bit 2 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to
zero when TCCR1A is written when operating in a PWM mode. When writing a logical
one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform
Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits
setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is
the value present in the COM1x1:0 bits that determine the effect of the forced compare.
COM1A1/COM1B1
COM1A1/COM1B1
(1)
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
0
0
1
1
0
0
1
1
set. In this case the compare match is ignored, but the set or clear is done at TOP.
See “Fast PWM Mode” on page 100. for more details.
set. See “Phase Correct PWM Mode” on page 102. for more details.
COM1A0/COM1B0
COM1A0/COM1B0
0
1
0
1
0
1
0
1
Description
Normal port operation, OC1A/OC1B
disconnected.
WGM13:0 = 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port
operation).
For all other WGM13:0 settings, normal port
operation, OCnA/OCnB disconnected.
Clear OC1A/OC1B on compare match, set
OC1A/OC1B at TOP
Set OC1A/OC1B on compare match, clear
OC1A/OC1B at TOP
Description
Normal port operation, OC1A/OC1B
disconnected.
WGM13:0 = 9 or 14: Toggle OCnA on
Compare Match, OCnB disconnected (normal
port operation).
For all other WGM13:0 settings, normal port
operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on compare match when
up-counting. Set OC1A/OC1B on compare
match when downcounting.
Set OC1A/OC1B on compare match when up-
counting. Clear OC1A/OC1B on compare
match when downcounting.
(1)
2466J–AVR–10/04