ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 178

• Manufacturer Part Number: ATMEGA16-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TWI Register Description
TWI Bit Rate Register – TWBR
TWI Control Register – TWCR
178
ATmega16(L)
• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a
frequency divider which generates the SCL clock frequency in the Master modes. See
“Bit Rate Generator Unit” on page 176 for calculating bit rates.
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to
initiate a Master access by applying a START condition to the bus, to generate a
receiver acknowledge, to generate a stop condition, and to control halting of the bus
while the data to be written to the bus are written to the TWDR. It also indicates a write
collision if data is attempted written to TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects appli-
cation software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will
jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is
stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note
that this flag is not automatically cleared by hardware when executing the interrupt rou-
tine. Also note that clearing this flag starts the operation of the TWI, so all accesses to
the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Regis-
ter (TWDR) must be complete before clearing this flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is writ-
ten to one, the ACK pulse is generated on the TWI bus if the following conditions are
met:
1. The device’s own Slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-
wire Serial Bus temporarily. Address recognition can then be resumed by writing the
TWEA bit to one again.
• Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the
Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a
START condition on the bus if it is free. However, if the bus is not free, the TWI waits
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TWBR7
TWINT
R/W
R/W
7
0
7
0
TWBR6
TWEA
R/W
R/W
6
0
6
0
TWBR5
TWSTA
R/W
R/W
5
0
5
0
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
R
3
0
3
0
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
TWBR0
TWIE
R/W
R/W
0
0
0
0
2466J–AVR–10/04
TWBR
TWCR