ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 135

• Manufacturer Part Number: ATMEGA16-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2466J–AVR–10/04
When configured as a Master, the SPI interface has no automatic control of the SS line.
This must be handled by user software before communication can start. When this is
done, writing a byte to the SPI Data Register starts the SPI clock generator, and the
hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener-
ator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit
(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue
to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high
the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for
later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated
as long as the SS pin is driven high. In this state, software may update the contents of
the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,
in the SPCR Register is set, an interrupt is requested. The Slave may continue to place
new data to be sent into SPDR before reading the incoming data. The last incoming byte
will be kept in the Buffer Register for later use.
Figure 66. SPI Master-Slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive
direction. This means that bytes to be transmitted cannot be written to the SPI Data
Register before the entire shift cycle is completed. When receiving data, however, a
received character must be read from the SPI Data Register before the next character
has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To
ensure correct sampling of the clock signal, the frequency of the SPI clock should never
exceed f
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is
overridden according to Table 55. For more details on automatic port overrides, refer to
“Alternate Port Functions” on page 53.
Table 55. SPI Pin Overrides
Pin
MOSI
MISO
SCK
SS
CLOCK GENERATOR
MSB
osc
8 BIT SHIFT REGISTER
/4.
SPI
Direction, Master SPI
User Defined
Input
User Defined
User Defined
MASTER
LSB
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
Direction, Slave SPI
Input
User Defined
Input
Input
MSB
8 BIT SHIFT REGISTER
ATmega16(L)
SLAVE
SHIFT
ENABLE
LSB
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