ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 154
![IC AVR MCU 16K 16MHZ 5V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA16-16PU
Manufacturer Part Number
ATMEGA16-16PU
Description
IC AVR MCU 16K 16MHZ 5V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA16L-8MI.pdf
(26 pages)
2.ATMEGA16L-8MI.pdf
(357 pages)
3.ATMEGA16-16PU.pdf
(358 pages)
4.ATMEGA16-16PU.pdf
(351 pages)
Specifications of ATMEGA16-16PU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
TWI/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA16x
Core
AVR8
Data Ram Size
1 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
16 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
4.5-5.5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16-16PU
Manufacturer:
Atmel
Quantity:
140
- ATMEGA16L-8MI PDF datasheet
- ATMEGA16L-8MI PDF datasheet #2
- ATMEGA16-16PU PDF datasheet #3
- ATMEGA16-16PU PDF datasheet #4
- Current page: 154 of 351
- Download datasheet (3Mb)
Receive Compete Flag and
Interrupt
Receiver Error Flags
Parity Checker
154
ATmega16(L)
The receive function example reads all the I/O Registers into the Register File before
any computation is done. This gives an optimal receive buffer utilization since the buffer
location read will be free to accept new data as early as possible.
The USART Receiver has one flag that indicates the receiver state.
The Receive Complete (RXC) Flag indicates if there are unread data present in the
receive buffer. This flag is one when unread data exist in the receive buffer, and zero
when the receive buffer is empty (i.e., does not contain any unread data). If the receiver
is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit
will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART
Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided
that global interrupts are enabled). When interrupt-driven data reception is used, the
receive complete routine must read the received data from UDR in order to clear the
RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
The USART Receiver has three Error Flags: Frame Error (FE), Data OverRun (DOR)
and Parity Error (PE). All can be accessed by reading UCSRA. Common for the Error
Flags is that they are located in the receive buffer together with the frame for which they
indicate the error status. Due to the buffering of the Error Flags, the UCSRA must be
read before the receive buffer (UDR), since reading the UDR I/O location changes the
buffer read location. Another equality for the Error Flags is that they can not be altered
by software doing a write to the flag location. However, all flags must be set to zero
when the UCSRA is written for upward compatibility of future USART implementations.
None of the Error Flags can generate interrupts.
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable
frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly
read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This
flag can be used for detecting out-of-sync conditions, detecting break conditions and
protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC
since the receiver ignores all, except for the first, stop bits. For compatibility with future
devices, always set this bit to zero when writing to UCSRA.
The Data OverRun (DOR) Flag indicates data loss due to a receiver buffer full condition.
A Data OverRun occurs when the receive buffer is full (two characters), it is a new char-
acter waiting in the receive Shift Register, and a new start bit is detected. If the DOR
Flag is set there was one or more serial frame lost between the frame last read from
UDR, and the next frame read from UDR. For compatibility with future devices, always
write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame
received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity
error when received. If parity check is not enabled the PE bit will always be read zero.
For compatibility with future devices, always set this bit to zero when writing to UCSRA.
For more details see “Parity Bit Calculation” on page 147 and “Parity Checker” on page
154.
The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type
of parity check to be performed (odd or even) is selected by the UPM0 bit. When
enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit from the serial frame. The result of the check is
stored in the receive buffer together with the received data and stop bits. The Parity
Error (PE) Flag can then be read by software to check if the frame had a parity error.
2466J–AVR–10/04
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