ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet - Page 188

• Manufacturer Part Number: ATMEGA16-16PU
• Description: IC AVR MCU 16K 16MHZ 5V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 16 MIPS
• Eeprom Memory: 512 Bytes
• Input Output: 32
• Interface: JTAG/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 16K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

188
ATmega16(L)
Figure 88. Data Transfer in Master Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be
written to one to transmit a START condition and TWINT must be set to clear the TWINT
Flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as
soon as the bus becomes free. After a START condition has been transmitted, the
TWINT Flag is set by hardware, and the status code in TWSR will be $08 (See Table
74). In order to enter MR mode, SLA+R must be transmitted. This is done by writing
SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to
continue the transfer. This is accomplished by writing the following value to TWCR:
When SLA+R have been transmitted and an acknowledgement bit has been received,
TWINT is set again and a number of status codes in TWSR are possible. Possible sta-
tus codes in Master mode are $38, $40, or $48. The appropriate action to be taken for
each of these status codes is detailed in Table 75. Received data can be read from the
TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated
until the last byte has been received. After the last byte has been received, the MR
should inform the ST by sending a NACK after the last received data byte. The transfer
is ended by generating a STOP condition or a repeated START condition. A STOP con-
dition is generated by writing the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state $10) the Two-wire Serial Interface can access
the same Slave again, or a new Slave without transmitting a STOP condition. Repeated
START enables the Master to switch between Slaves, Master Transmitter mode and
Master Receiver mode without losing control over the bus.
TWCR
Value
TWCR
Value
TWCR
Value
TWCR
Value
SDA
SCL
TWINT
TWINT
TWINT
TWINT
Device 1
RECEIVER
1
1
1
1
MASTER
TWEA
TWEA
TWEA
TWEA
X
X
X
X
TRANSMITTER
Device 2
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
1
Device 3
TWSTO
TWSTO
TWSTO
TWSTO
0
0
1
0
........
TWWC
TWWC
TWWC
TWWC
X
X
X
X
Device n
TWEN
TWEN
TWEN
TWEN
V
1
1
1
1
CC
R1
–
0
–
0
–
0
–
0
2466J–AVR–10/04
R2
TWIE
TWIE
TWIE
TWIE
X
X
X
X