ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet

IC AVR MCU 16K 16MHZ 5V 40DIP

ATMEGA16-16PU

Manufacturer Part Number
ATMEGA16-16PU
Description
IC AVR MCU 16K 16MHZ 5V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA16-16PU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
TWI/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA16x
Core
AVR8
Data Ram Size
1 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
16 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
4.5-5.5 V
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA16-16PU
Manufacturer:
Atmel
Quantity:
140
Features
High-performance, Low-power AVR
Advanced RISC Architecture
Nonvolatile Program and Data Memories
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 16K Bytes of In-System Self-Programmable Flash
– Optional Boot Code Section with Independent Lock Bits
– 512 Bytes EEPROM
– 1K Byte Internal SRAM
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF
– 2.7 - 5.5V for ATmega16L
– 4.5 - 5.5V for ATmega16
– 0 - 8 MHz for ATmega16L
– 0 - 16 MHz for ATmega16
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 µA
Mode
and Extended Standby
Endurance: 10,000 Write/Erase Cycles
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Endurance: 100,000 Write/Erase Cycles
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
8-bit Microcontroller
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega16
ATmega16L
2466J–AVR–10/04

Related parts for ATMEGA16-16PU

ATMEGA16-16PU Summary of contents

Page 1

... ATmega16L – 4.5 - 5.5V for ATmega16 • Speed Grades – MHz for ATmega16L – MHz for ATmega16 • Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA ® 8-bit Microcontroller 8-bit ...

Page 2

... Pin Configurations Disclaimer ATmega16(L) 2 Figure 1. Pinout ATmega16 (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 (MOSI) PB5 ...

Page 3

... Overview Block Diagram 2466J–AVR–10/04 The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...

Page 4

... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16 as listed on page 56. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... AVR CPU Core Introduction Architectural Overview ATmega16(L) 6 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3. Block Diagram of the AVR MCU Architecture ...

Page 7

... The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit Read/Write R/W R/W R/W Initial Value ATmega16( R/W R/W R/W R/W R ...

Page 8

... ATmega16(L) 8 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings ...

Page 9

... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. ATmega16(L) 0 Addr. R0 ...

Page 10

... The X-register, Y-register and Z-register Stack Pointer ATmega16(L) 10 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. ...

Page 11

... Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 43. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 ATmega16(L) , directly generated from the selected clock CPU ...

Page 12

... ATmega16(L) 12 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 43 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “ ...

Page 13

... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega16(L) 13 ...

Page 14

... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16 Program Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...

Page 15

... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of inter- nal data SRAM in the ATmega16 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 9. ...

Page 16

... Data RD Memory Access Instruction The ATmega16 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

Page 17

... X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...

Page 18

... ATmega16(L) 18 When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM ...

Page 19

... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega16(L) 19 ...

Page 20

... EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption ATmega16(L) 20 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ...

Page 21

... The I/O space definition of the ATmega16 is shown in “Register Summary” on page 331. All ATmega16 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general pur- pose working registers and the I/O space ...

Page 22

... I/O Clock – clk I/O Flash Clock – clk FLASH ATmega16(L) 22 Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “ ...

Page 23

... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscil- lator is voltage dependent as shown in “ATmega16 Typical Characteristics” on page 299. Table 3. Number of Watchdog Oscillator Cycles Typ Time-out ( ...

Page 24

... ATmega16(L) 24 This mode has a limited frequency range and it can not be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environ- ment ...

Page 25

... These options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. ATmega16(L) Additional Delay from Reset ( ...

Page 26

... Low-frequency Crystal Oscillator External RC Oscillator ATmega16( use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors ...

Page 27

... Note: 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC). ATmega16(L) Frequency Range (MHz) 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 Additional Delay ...

Page 28

... Oscillator Calibration Register – OSCCAL ATmega16(L) 28 Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power-down and SUT1..0 Power-save ( Note: 1. The device is shipped with this option selected. Bit CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value Device Specific Calibration Value • ...

Page 29

... For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. ATmega16(L) Additional Delay from Reset ( ...

Page 30

... If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 22 presents the different clock systems in the ATmega16, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. ...

Page 31

... Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec- ommended instead of Power-save mode because the contents of the registers in the ATmega16(L) and clk , while allowing the other CPU ...

Page 32

... External Crystal or resonator selected as clock source bit in ASSR is set. 3. Only INT2 or level interrupt INT1 and INT0. ATmega16(L) 32 Asynchronous Timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk chronous modules, including Timer/Counter2 if clocked asynchronously. ...

Page 33

... Enable and Sleep Modes” on page 52 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V /2, the input buffer will use excessive power. CC ATmega16(L) ) and the ADC clock (clk ) are stopped, the I/O ADC ...

Page 34

... JTAG Interface and On-chip Debug System ATmega16( the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • ...

Page 35

... The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 23. The ATmega16 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...

Page 36

... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega16L and BODLEVEL = 0 for ATmega16. BODLEVEL = 1 is not applicable for ATmega16. DATA BUS ...

Page 37

... V CC Figure 16. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 17. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET ATmega16(L) rise. The RESET signal is activated CC decreases below the detection level RST t TOUT is below the CC 37 ...

Page 38

... MCU after the Time-out period t Figure 18. External Reset During Operation CC ATmega16 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed ...

Page 39

... To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. ATmega16( ...

Page 40

... Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega16 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 39. ...

Page 41

... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...

Page 42

... ATmega16(L) 42 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example WDT_off: ; Reset WDT WDR ...

Page 43

... Interrupts Interrupt Vectors in ATmega16 2466J–AVR–10/04 This section describes the specifics of the interrupt handling as performed in ATmega16. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11. Table 18. Reset and Interrupt Vectors Program (2) Vector No. Address Source (1) 1 $000 ...

Page 44

... Note: 1. The Boot Reset Address is shown in Table 100 on page 257. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16 is: Address Labels Code ...

Page 45

... SPH,r16 $1C2C ldi r16,low(RAMEND) $1C2D out SPL,r16 $1C2E sei $1C2F <instr> ATmega16(L) Comments ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...

Page 46

... Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR ATmega16(L) 46 The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit INT1 INT0 INT2 Read/Write R/W R/W R/W Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory ...

Page 47

... Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret C Code Example void Move_interrupts(void Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); } ATmega16(L) 47 ...

Page 48

... I/O Ports Introduction ATmega16(L) 48 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input) ...

Page 49

... When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up ATmega16( DDxn ...

Page 50

... Reading the Pin Value ATmega16(L) 50 enabled state is fully acceptable high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11 intermediate step ...

Page 51

... In this case, the delay t clock period. Figure 25. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 ATmega16(L) and t pd,max through the synchronizer is one system pd 0xFF nop in r17, PINx 0x00 t ...

Page 52

... Digital Input Enable and Sleep Modes ATmega16(L) 52 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins ...

Page 53

... SLEEP CONTROL Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega16(L) or GND is not recommended, since this may CC (1) ...

Page 54

... ATmega16(L) 54 Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 21. Generic Description of Overriding Signals for Alternate Functions ...

Page 55

... Table 23 and Table 24 relate the alternate functions of Port A to the overriding signals shown in Figure 26 on page 53. Table 23. Overriding Signals for Alternate Functions in PA7..PA4 Signal Name PA7/ADC7 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ADC7 INPUT ATmega16( – ACME PUD PSR2 R R/W R/W R PA6/ADC6 PA5/ADC5 ...

Page 56

... Alternate Functions of Port B ATmega16(L) 56 Table 24. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/ADC3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE 0 DIEOV 0 DI – AIO ADC3 INPUT The Port B pins with alternate functions are shown in Table 25. Table 25. Port B Pins Alternate Functions ...

Page 57

... USART operates in Synchronous mode. Table 26 and Table 27 relate the alternate functions of Port B to the overriding signals shown in Figure 26 on page 53. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATmega16(L) 57 ...

Page 58

... ATmega16(L) 58 Table 26. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD DDOE SPE • MSTR SPE • MSTR DDOV 0 0 PVOE SPE • MSTR SPE • MSTR ...

Page 59

... The TD0 pin is tri-stated unless TAP states that shifts out data are entered. • TMS – Port C, Bit 3 TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. ATmega16(L) 59 ...

Page 60

... ATmega16(L) 60 • TCK – Port C, Bit 2 TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG inter- face is enabled, this pin can not be used as an I/O pin. • SDA – Port C, Bit 1 SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface ...

Page 61

... The OC2 pin is also the output pin for the PWM mode timer function. • ICP1 – Port D, Bit 6 ICP1 – Input Capture Pin: The PD6 pin can act as an Input Capture pin for Timer/Counter1. ATmega16(L) (1) PC1/SDA PC0/SCL TWEN TWEN PORTC1 • ...

Page 62

... ATmega16(L) 62 • OC1A – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • ...

Page 63

... Table 33. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PD3/INT1 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 DIEOE INT1 ENABLE DIEOV 1 DI INT1 INPUT AIO – ATmega16(L) PD2/INT0 PD1/TXD PD0/RXD 0 TXEN RXEN 0 0 PORTD0 • PUD 0 TXEN RXEN TXEN 0 0 TXD 0 INT0 ENABLE ...

Page 64

... Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB ATmega16(L) 64 Bit PORTA7 PORTA6 PORTA5 Read/Write R/W ...

Page 65

... R/W R/W R/W Initial Value Bit DDD7 DDD6 DDD5 Read/Write R/W R/W R/W Initial Value Bit PIND7 PIND6 PIND5 Read/Write Initial Value N/A N/A N/A ATmega16( PORTC4 PORTC3 PORTC2 PORTC1 R/W R/W R/W R DDC4 DDC3 DDC2 DDC1 R/W R/W R/W R PINC4 ...

Page 66

... External Interrupts MCU Control Register – MCUCR ATmega16(L) 66 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register – ...

Page 67

... Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ATmega16( JTRF WDRF ...

Page 68

... General Interrupt Flag Register – GIFR ATmega16(L) 68 ISC10) in the MCU General Control Register (MCUCR) define whether the External Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 inter- rupt Vector ...

Page 69

... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the actual placement of I/O pins, refer to “Pinout ATmega16” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...

Page 70

... Definitions Timer/Counter Clock Sources Counter Unit ATmega16(L) 70 The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the wave- form generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 71. for details. The compare match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request ...

Page 71

... Figure 29 shows a block diagram of the output compare unit. Figure 29. Output Compare Unit, Block Diagram OCRn = top bottom Waveform Generator FOCn WGMn1:0 ATmega16(L) ). clk can be generated from an external or internal T0 is present or not. A CPU write overrides (has T0 DATA BUS TCNTn (8-bit Comparator ) COMn1:0 OCFn (Int ...

Page 72

... Using the Output Compare Unit Compare Match Output Unit ATmega16(L) 72 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence ...

Page 73

... Table 40 on page 82, and for phase correct PWM refer to Table 41 on page 82. A change of the COM01:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. ATmega16( OCn ...

Page 74

... Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega16(L) 74 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do ...

Page 75

... PWM mode is shown in Figure 32. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. ATmega16(L) f clk_I/O = ---------------------------------------------- - ⋅ ...

Page 76

... ATmega16(L) 76 Figure 32. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin ...

Page 77

... The PWM waveform is generated by clearing (or setting) the OC0 Register at the compare match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between ATmega16(L) OCn Interrupt Flag Set OCRn Update ...

Page 78

... ATmega16(L) 78 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCnPCPWM The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode ...

Page 79

... Figure 35 shows the same timing data, but with the prescaler enabled. Figure 35. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 36 shows the setting of OCF0 in all modes except CTC mode. ATmega16(L) T0 MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM ) is therefore BOTTOM + 1 79 ...

Page 80

... ATmega16(L) 80 Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f /8) ...

Page 81

... These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to the OC0 pin must be set in order to enable the output driver. ATmega16( ...

Page 82

... ATmega16(L) 82 When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 39 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 39. Compare Output Mode, non-PWM Mode COM01 COM00 ...

Page 83

... Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is ATmega16(L) /(No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler) ...

Page 84

... Timer/Counter Interrupt Flag Register – TIFR ATmega16(L) 84 executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled ...

Page 85

... Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less ATmega16(L) ). Alternatively, one of four taps from the pres- CLK_I/O /1024. ...

Page 86

... Special Function IO Register – SFIOR ATmega16(L) 86 than half the system clock frequency (f the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock frequency and duty cycle caused by Oscillator source (crystal, ...

Page 87

... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to Figure 1 on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 109. ATmega16(L) 87 ...

Page 88

... Registers ATmega16(L) 88 Figure 40. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 25 on page 56, and Table 31 on page 61 for Timer/Counter1 pin placement and description. The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “ ...

Page 89

... PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega16(L) 89 ...

Page 90

... Accessing 16-bit Registers ATmega16(L) 90 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access ...

Page 91

... SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. The example code assumes that the part specific header file is included. The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega16(L) 91 ...

Page 92

... Reusing the Temporary High Byte Register Timer/Counter Clock Sources ATmega16(L) 92 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt flag ...

Page 93

... Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 99. The Timer/Counter Overflow (TOV1) Flag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. ATmega16(L) TOVn (Int.Req.) Clock Select Count ...

Page 94

... Input Capture Unit ATmega16(L) 94 The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied ...

Page 95

... ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). ATmega16(L) 95 ...

Page 96

... Output Compare Units ATmega16(L) 96 The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an output compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed ...

Page 97

... Normal mode. The OC1x Register keeps its value even when changing between waveform generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATmega16(L) 97 ...

Page 98

... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega16(L) 98 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig- ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting ...

Page 99

... This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 45. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATmega16(L) 99 ...

Page 100

... Fast PWM Mode ATmega16(L) 100 Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 1 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value ...

Page 101

... TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. ATmega16( ...

Page 102

... Phase Correct PWM Mode ATmega16(L) 102 The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around start- ing at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered ...

Page 103

... The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall- ATmega16( ...

Page 104

... Phase and Frequency Correct PWM Mode ATmega16(L) 104 ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output ...

Page 105

... OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non- ATmega16(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) ...

Page 106

... Timer/Counter Timing Diagrams ATmega16(L) 106 inverted PWM and an inverted PWM output can be generated by setting the COM1x1 (See Table on page 110). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is ...

Page 107

... TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) Figure 52 shows the same timing data, but with the prescaler enabled. ATmega16(L) OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O ...

Page 108

... ATmega16(L) 108 Figure 52. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP ...

Page 109

... WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 44. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. ATmega16( COM1B0 FOC1A FOC1B WGM11 R R/W 0 ...

Page 110

... ATmega16(L) 110 Table 45. Compare Output Mode, Fast PWM COM1A1/COM1B1 COM1A0/COM1B0 Note special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 100. for more details. ...

Page 111

... PWM, Phase and Frequency Correct 1 0 PWM, Phase Correct 1 1 PWM, Phase Correct 0 0 CTC 0 1 Reserved 1 0 Fast PWM 1 1 Fast PWM ATmega16(L) Update of TOV1 Flag Set x TOP OCR1 on 0xFFFF Immediate MAX 0x00FF TOP BOTTOM 0x01FF TOP BOTTOM 0x03FF TOP BOTTOM ...

Page 112

... Timer/Counter1 Control Register B – TCCR1B ATmega16(L) 112 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output ...

Page 113

... The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 90. ATmega16( ...

Page 114

... Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK ATmega16(L) 114 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value ...

Page 115

... TOV1 Flag is set when the timer overflows. Refer to Table 47 on page 111 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega16( ...

Page 116

... Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the actual placement of I/O pins, refer to “Pinout ATmega16” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...

Page 117

... Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock. T2 ATmega16( default equal to the MCU clock, clk T2 TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler top . ...

Page 118

... Output Compare Unit ATmega16(L) 118 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T2 clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped ...

Page 119

... Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. ATmega16(L) 119 ...

Page 120

... Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega16(L) 120 The Compare Output mode (COM21:0) bits have two functions. The Waveform Genera- tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next compare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 56 shows a simplified schematic of the logic affected by the COM21:0 bit setting ...

Page 121

... OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOT- TOM when the counter is running with none or a low prescaler value must be done with ATmega16(L) OCn Interrupt Flag Set 2 ...

Page 122

... Fast PWM Mode ATmega16(L) 122 care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the com- pare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur ...

Page 123

... Figure 59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. ATmega16( set each time the counter reaches MAX. If TOV2 f ...

Page 124

... ATmega16(L) 124 Figure 59. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag ( TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin ...

Page 125

... Figure 61 shows the same timing data, but with the prescaler enabled. Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 62 shows the setting of OCF2 in all modes except CTC mode. ATmega16(L) MAX BOTTOM /8) clk_I/O MAX BOTTOM should I/O BOTTOM + 1 BOTTOM + 1 125 ...

Page 126

... ATmega16(L) 126 Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f ...

Page 127

... These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to OC2 pin must be set in order to enable the output driver. ATmega16( ...

Page 128

... ATmega16(L) 128 When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 51 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 51. Compare Output Mode, non-PWM Mode COM21 ...

Page 129

... Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt generate a waveform output on the OC2 pin. ATmega16(L) Description No clock source (Timer/Counter stopped). clk /(No prescaling) T2S clk /8 (From prescaler) ...

Page 130

... Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 ATmega16(L) 130 Bit – – – Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk AS2 is written to one, Timer/Counter2 is clocked from a Crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin ...

Page 131

... Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up ATmega16(L) 131 ...

Page 132

... Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR ATmega16(L) 132 from Power-save mode, and the I/O clock (clk read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time ...

Page 133

... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. ATmega16(L) 10-BIT T/C PRESCALER Clear 0 ...

Page 134

... Serial Peripheral Interface – SPI ATmega16(L) 134 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16 and peripheral devices or between several AVR devices. The ATmega16 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...

Page 135

... Table 55. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 53. Table 55. SPI Pin Overrides Pin Direction, Master SPI MOSI User Defined MISO Input SCK User Defined SS User Defined ATmega16(L) MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SCK SCK SS SS Direction, Slave SPI ...

Page 136

... ATmega16(L) 136 Note: See “Alternate Functions of Port B” on page 56 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins ...

Page 137

... Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; } Note: 1. The example code assumes that the part specific header file is included. ATmega16(L) 137 ...

Page 138

... SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega16(L) 138 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data ...

Page 139

... SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: osc Table 58. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 ATmega16(L) Trailing Edge Trailing Edge Setup SPR0 SCK Frequency osc osc osc f / ...

Page 140

... CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran- teed to work lower. osc The SPI interface on the ATmega16 is also used for program memory and EEPROM downloading or uploading. See page 273 for SPI Serial Programming and Verification. Bit 7 ...

Page 141

... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB ATmega16(L) Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...

Page 142

... USART Overview ATmega16(L) 142 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • ...

Page 143

... U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Figure 70 shows a block diagram of the clock generation logic. ATmega16(L) 143 ...

Page 144

... Internal Clock Generation – The Baud Rate Generator ATmega16(L) 144 Figure 70. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). ...

Page 145

... XCK clock frequency is limited by the following equation: Note that f depends on the stability of the system clock source therefore recom- osc mended to add some margin to avoid possible loss of data due to frequency variations. ATmega16(L) Equation for Equation for Calculating Calculating UBRR (1) Baud Rate ...

Page 146

... Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock Frame Formats ATmega16(L) 146 input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed ...

Page 147

... For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC. ATmega16(L) ⊕ … ⊕ ...

Page 148

... Sending Frames with Data Bit ATmega16(L) 148 (1) Assembly Code Example USART_Init: ; Set baud rate UBRRH, r17 out out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<<RXEN)|(1<<TXEN) out UCSRB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0) ...

Page 149

... The example code assumes that the part specific header file is included. The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty Inter- rupt is utilized, the interrupt routine writes the data into the buffer. ATmega16(L) 149 ...

Page 150

... Sending Frames with 9 Data Bit Transmitter Flags and Interrupts ATmega16(L) 150 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16 ...

Page 151

... The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD pin. ATmega16(L) 151 ...

Page 152

... Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega16(L) 152 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input ...

Page 153

... If error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: 1. The example code assumes that the part specific header file is included. ATmega16(L) 153 ...

Page 154

... Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker ATmega16(L) 154 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ...

Page 155

... Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). ATmega16(L) 155 ...

Page 156

... Asynchronous Data Recovery ATmega16(L) 156 Figure 73. Start Bit Sampling RxD IDLE Sample (U2X = Sample (U2X = When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam- ple as shown in the figure ...

Page 157

... Double Speed mode the ratio of the slowest incoming data rate that can be accepted in relation to the slow receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. ATmega16(L) STOP 1 (A) ( 0/1 ...

Page 158

... ATmega16(L) 158 Table 61 and Table 62 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) ...

Page 159

... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega16(L) 159 ...

Page 160

... Accessing UBRRH/ UCSRC Registers Write Access Read Access ATmega16(L) 160 The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written ...

Page 161

... The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. ATmega16( ...

Page 162

... USART Control and Status Register A – UCSRA ATmega16(L) 162 Bit RXC TXC UDRE Read/Write R R/W R Initial Value • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is dis- abled, the receive buffer will be flushed and consequently the RXC bit will become zero ...

Page 163

... Size frame the receiver and transmitter use. • Bit 1 – RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. ATmega16( ...

Page 164

... USART Control and Status Register C – UCSRC ATmega16(L) 164 • Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. ...

Page 165

... UBRRH. The URSEL must be zero when writing the UBRRH. • Bit 14:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. ATmega16(L) UCSZ0 Character Size 0 ...

Page 166

... UBRR = 0, Error = 0.0% ATmega16(L) 166 • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the 8 least significant bits of the USART baud rate ...

Page 167

... ATmega16( 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...

Page 168

... Max 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATmega16(L) 168 11.0592 f = osc U2X = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...

Page 169

... Mbps 1.152 Mbps ATmega16( 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...

Page 170

... Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology ATmega16(L) 170 • Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device Can Operate as Transmitter or Receiver • 7-bit Address Space allows up to 128 Different Slave Addresses • ...

Page 171

... START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. ATmega16(L) Data Stable Data Change 171 ...

Page 172

... Address Packet Format ATmega16(L) 172 Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation performed, otherwise a write operation should be per- formed ...

Page 173

... Figure 81 shows a typical data transmission. Note that several data bytes can be trans- mitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software. Figure 81. Typical Data Transmission Addr MSB Addr LSB R/W SDA SCL START SLA+R/W ATmega16(L) Data LSB ACK Data Byte ACK Data MSB Data LSB ...

Page 174

... Multi-master Bus Systems, Arbitration and Synchronization ATmega16(L) 174 The TWI protocol allows bus systems with several Masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more Masters initiate a transmission at the same time. Two problems arise in multi-mas- ter systems: • ...

Page 175

... This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATmega16(L) Master A Loses Arbitration, SDA SDA ...

Page 176

... Overview of the TWI Module SCL and SDA Pins Bit Rate Generator Unit ATmega16(L) 176 The TWI module is comprised of several submodules, as shown in Figure 84. All regis- ters drawn in a thick line are accessible through the AVR data bus. Figure 84. Overview of the TWI Module ...

Page 177

... After the TWI has been addressed by own Slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition ATmega16(L) 177 ...

Page 178

... TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR ATmega16(L) 178 Bit TWBR7 TWBR6 TWBR5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See “ ...

Page 179

... Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. ATmega16( ...

Page 180

... TWI Data Register – TWDR TWI (Slave) Address Register – TWAR ATmega16(L) 180 • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 73. TWI Bit Rate Prescaler TWPS1 TWPS0 calculate bit rates, see “Bit Rate Generator Unit” on page 176. The value of TWPS1 ...

Page 181

... When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. ATmega16(L) 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control ...

Page 182

... ATmega16(L) 182 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates other- wise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR ...

Page 183

... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega16(L) Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits ...

Page 184

... Transmission Modes Master Transmitter Mode ATmega16(L) 184 The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM ...

Page 185

... STOP condition or a repeated START condition. A STOP condition is gen- erated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value 1 X ATmega16( ........ Device 3 Device n TWSTO TWWC TWEN TWSTO TWWC TWEN 0 ...

Page 186

... NOT ACK has been received $38 Arbitration lost in SLA+W or data bytes ATmega16(L) 186 After a repeated START condition (state $10) the Two-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus ...

Page 187

... The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. ATmega16( DATA ...

Page 188

... ATmega16(L) 188 Figure 88. Data Transfer in Master Receiver Mode Device 1 Device 2 MASTER SLAVE RECEIVER TRANSMITTER SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag ...

Page 189

... Read data byte Read data byte Read data byte ATmega16(L) TWEA Next Action Taken by TWI Hardware X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to masTer Transmitter mode ...

Page 190

... Slave Receiver Mode ATmega16(L) 190 Figure 89. Formats and States in the Master Receiver Mode MR Successfull S SLA R A reception from a slave receiver $08 $40 Next transfer started with a repeated start condition Not acknowledge A received after the slave address $48 Arbitration lost in slave address or data byte ...

Page 191

... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. ATmega16(L) TWSTA TWSTO TWWC ...

Page 192

... Previously addressed with general call; data has been received; NOT ACK has been returned $A0 A STOP condition or repeated START condition has been received while still addressed as Slave ATmega16(L) 192 Application Software Response To TWCR To/from TWDR STA STO TWINT No TWDR action or X ...

Page 193

... Figure 92. Data Transfer in Slave Transmitter Mode Device 1 Device 2 SLAVE MASTER TRANSMITTER RECEIVER SDA SCL To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 Value ATmega16( DATA A DATA $60 $80 A $68 A DATA A DATA $70 ...

Page 194

... ATmega16(L) 194 The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWCR TWINT TWEA ...

Page 195

... No TWDR action TWDR action TWDR action ATmega16(L) TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should be received ...

Page 196

... Bus and Two-wire Serial Inter- are 0 face Hardware $F8 No relevant state information available; TWINT = “0” $00 Bus error due to an illegal START or STOP condition ATmega16(L) 196 Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own S SLA R slave address and one or more data bytes ...

Page 197

... An example of an arbitration situation is depicted below, where two Masters are trying to transmit data to a Slave Receiver. Figure 95. An Arbitration Example Device 1 Device 2 MASTER MASTER TRANSMITTER TRANSMITTER SDA SCL ATmega16(L) Master Receiver A Rs SLA+R A DATA Rs = REPEATED START Transmitted from Slave to Master V CC Device 3 ...

Page 198

... ATmega16(L) 198 Several different scenarios may arise during arbitration, as described below: • Two or more Masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the Masters will know about the bus contention. • Two or more Masters are accessing the same Slave with different data or direction bit ...

Page 199

... When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar- ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 201. ATmega16(L) ( ...

Page 200

... Analog Comparator Control and Status Register – ACSR ATmega16(L) 200 Bit ACD ACBG ACO Read/Write R/W R/W R Initial Value 0 0 N/A • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. ...

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