DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 76

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 8-26
the ATM device places address ‘00h’ on the address bus (which is mapped to Port 1). PHY device '1' (Port 1)
indicates to the ATM device that it has a complete cell to send by asserting RDXA[1]. On clock edge 4, the ATM
device selects PHY device '1'. On clock edge 5, the ATM device asserts REN. On clock edge 6, the PHY device ‘1’
starts a cell transfer to the ATM device by placing the first byte of cell data on RDATA, and asserting RSOX to
indicate the transfer of the first byte of the cell. On clock edge 7, the PHY device deasserts RSOX as it continues to
place additional bytes of the cell on RDATA. On clock edge 13, PHY device ‘2’ asserts RDXA[2] to indicate to the
ATM device that it is ready to send a cell. On clock edge 15, PHY device '1’ indicates that it cannot transfer a
complete cell by deasserting RDXA[1]. On clock edge 16, the ATM device deselects PHY device '1' and selects
PHY device '2' by deasserting REN and placing PHY device '2's address on RADR. On clock edge 17, the ATM
device asserts REN. On clock edge 18, PHY device ‘2’ (Port 2) starts the transfer of a cell to the ATM device by
placing the first byte of cell data on RDATA, and asserting RSOX to indicate the transfer of the first byte of the cell.
On clock edge 18, the PHY device deasserts RSOX as it continues to place additional bytes of the cell on RDATA.
Figure 8-26. UTOPIA Level 2 Receive Cell Transfer Direct Mode
Figure 8-27
the ATM device polls PHY device 'N'. On clock edge 3, PHY device 'N' indicates to the ATM device that it can
accept cell data by asserting TPXA. On clock edge 4, the ATM device selects PHY device 'N'. On clock edge 5, the
ATM device starts a cell transfer to PHY device 'N' by asserting TEN, placing the first byte of cell data on TDATA,
and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 6, the ATM device deasserts
TSOX as it continues to place additional bytes of the cell on TDATA. On clock edge 6, the ATM device also polls
PHY device 'O'. On clock edge 7, PHY device 'O' indicates that it can accept the transfer of a complete cell. On
clock edge 14, the ATM device polls PHY device 'N'. On clock edge 15, PHY device 'N' indicates that it cannot
accept the transfer of a complete cell. On clock edge 16, the ATM device deselects PHY device 'N' and selects
PHY device 'O' by deasserting TEN and placing PHY device 'O's address on TADR. On clock edge 17, the ATM
device starts the transfer of a cell to PHY device 'O' by asserting TEN, placing the first byte of cell data on TDATA,
and asserting TSOX to indicate the transfer of the first byte of the cell. On clock edge 18, the ATM device
deasserts TSOX as it continues to place additional bytes of the cell on TDATA.
RDXA[2]
RDXA[1]
RDXA[3]
RDXA[4]
RDATA
RSCLK
Cell From:
RADR
Transfer
RSOX
REN
shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2,
shows a multidevice transmit-interface multiple cell transfer to different PHY devices. On clock edge 2,
1
2
3
4
5
6
H1
7
H2
…
8
00h
H3
9
76
10
P42
11
PORT 1
P43
12
P44
13
P45
14
P46
15
P47
16
P48
17
01h
18
H1
PORT 2
19
H2
20
H3