DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 260

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.7.2 HDLC Receive Side Register Map
The receive side uses five registers.
Table 12-28. Receive Side HDLC Register Map
12.7.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 8: Receive HDLC Data Available Level (RDAL[4:0]) – These five bits indicate the minimum number of
eight byte groups that must be stored (contain data) in the Receive FIFO before HDLC data is considered to be
available (RHDA=1). For example, a value of 21 (15h) results in HDLC data being available when the Receive
FIFO contains 168 (A8h) bytes or more.
Bit 3: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is in the
LSB of the Receive FIFO Data byte RFD[0]). When 1, bit reordering is enabled (The first bit received is in the MSB
of the Receive FIFO Data byte RFD[7]).
Bit 2: Receive Data Inversion Enable (RDIE) – When 0, the incoming data is directly passed on for packet
processing. When 1, the incoming data is inverted before being passed on for packet processing.
Bit 1: Receive FCS Processing Disable (RFPD) – When 0, FCS processing is performed (the packets have a
FCS appended). When 1, FCS processing is disabled (the packets do not have a FCS appended).
Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, however, data is
discarded until a start of packet is received after RAM power-up is completed. When 1, the Receive FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the RHDA bit is forced low, and all
incoming data is discarded.
(0,2,4,6)BCh
(0,2,4,6)BAh
(0,2,4,6)BEh
(0,2,4,6)B0h
(0,2,4,6)B2h
(0,2,4,6)B4h
(0,2,4,6)B6h
(0,2,4,6)B8h
ADDRESS
15
—
—
0
7
0
HDLC.RSRIE
HDLC.RFDR
HDLC.RSRL
HDLC.RCR
REGISTER
HDLC.RSR
—
—
—
14
—
—
0
6
0
HDLC Receive Control Register
Unused
HDLC Receive Status Register
HDLC Receive Status Register Latched
HDLC Receive Status Register Interrupt Enable
Unused
HDLC Receive FIFO Data Register
Unused
HDLC.RCR
HDLC Receive Control Register
(0,2,4,6)B0h
13
—
—
0
5
0
REGISTER DESCRIPTION
RDAL4
12
—
0
0
4
260
RDAL3
RBRE
11
1
3
0
RDAL2
RDIE
10
0
2
0
RDAL1
RFPD
9
0
1
0
RFRST
RDAL0
8
0
0
0