DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 265

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 13 to 8: Transmit FEAC Code B (TFCB[5:0]) – These six bits are the transmit FEAC code B data to be
stored inserted into codeword B. TFCB[5] is the LSB (last bit transmitted) of the FEAC code (C[6]), and TFCB[0] is
the MSB (first bit transmitted) of the FEAC code (C[1]).
Bits 5 to 0: Transmit FEAC Code A (TFCA[5:0]) – These six bits are the transmit FEAC code A data to be stored
inserted into codeword A. TFCA[5] is the LSB (last bit transmitted) of the FEAC code (C[6]), and TFCA[0] is the
MSB (first bit transmitted) of the FEAC code (C[1]).
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Transmit FEAC Idle (TFI) – When 0, the Transmit FEAC processor is sending a FEAC codeword. When 1,
the Transmit FEAC processor is sending an Idle signal (all ones).
15
15
—
—
—
—
0
7
0
7
14
14
—
—
—
—
0
6
0
6
FEAC.TFDR
FEAC Transmit Data Register
(0,2,4,6)C2h
FEAC.TSR
FEAC Transmit Status Register
(0,2,4,6)C4h
TFCB5
TFCA5
13
13
—
—
0
5
0
5
TFCB4
TFCA4
12
12
—
—
0
0
4
4
265
TFCB3
TFCA3
11
11
—
—
0
3
0
3
TFCB2
TFCA2
10
10
—
—
0
2
0
2
TFCB1
TFCA1
—
—
9
0
1
0
9
1
TFCB0
TFCA0
TFI
—
8
0
0
0
8
0