DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 355

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Receive Corrected Header Count (RCHC[23:16]) - Upper 8 bits of Register.
Receive Corrected Header Count (RCHC[23:0]) – These 24 bits indicate the number of cells that have had
header errors corrected. If header error correction is disabled, this count will be zero. This count will be included in
the receive cell count registers (CP.RCCR), receive filtered idle/unassigned/invalid cell count registers
(CP.RFCCR), or receive header pattern cell count registers (CP.RHPCR). This register is updated via the PMU
signal (see Section 10.4.5).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Filtered Cell Count (RFCC[15:0]) – Lower 16 bits of 24 bits. Register description follows
next register.
RCHC23
RFCC15
RFCC7
15
15
—
0
7
0
0
7
0
RCHC22
RFCC14
RFCC6
14
14
—
CP.RFCCR1
Cell Processor Receive Filtered Idle/Unassigned/Invalid Cell Count Register 1
(1,3,5,7)E4h
0
6
0
0
6
0
CP.RCCCR2
Cell Processor Receive Corrected Cell Count Register 2
(1,3,5,7)E2h
RCHC21
RFCC13
RFCC5
13
13
—
0
5
0
0
5
0
RCHC20
RFCC12
RFCC4
12
12
—
0
0
0
0
4
4
355
RCHC19
RFCC11
RFCC3
11
11
—
0
3
0
0
3
0
RCHC18
RFCC10
RFCC2
10
10
—
0
2
0
0
2
0
RCHC17
RFCC9
RFCC1
—
9
0
1
0
9
0
1
0
RCHC16
RFCC8
RFCC0
—
8
0
0
0
8
0
0
0