DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 399

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.9 JTAG Interface AC Characteristics
All AC timing characteristics are specified with a 50pF capacitive load on JTDO pin and 25pF capacitive load on all
other digital output pins, V
generic timing definitions shown
interface.
Table 18-17. JTAG Interface Timing
(V
Note 1:
Note 2:
Note 3:
JTCLK
JTCLK
JTCLK
JTMS and JTDI
JTMS and JTDI
JTDO
JTDO
JTDO
Any Digital Output
Any Digital Output
Any Digital Output
Any Digital Output
Any Digital Output
Any Digital Output
DD
SIGNAL NAME(S)
= 3.3V ±5%, T
Change during Update-DR state.
Change during Update-IR state to or from EXTEST mode.
Change during Update-IR state to or from HIZ mode.
j
= -40°C to +125°C.)
SYMBOL
IH
= 2.4V and V
f1
t2
t3
t5
t6
t7
t8
t9
t7
t7
t8
t9
t8
t9
Figure
Clock frequency (1/t1)
Clock high or low period
Rise/fall times
Hold time from JTCLK rising edge
Setup time to JTCLK rising edge
Delay from JTCLK falling edge
Delay out of high-Z from JTCLK falling
edge
Delay to high-Z from JTCLK falling edge
Delay from JTCLK falling edge (Note 1)
Delay out of high-Z from JTCLK falling
edge (Note 1)
Delay into high-Z from JTCLK falling
edge (Note 1)
Delay out of high-Z from JTCLK rising
edge (Notes 2, 3)
Delay into high-Z from JTCLK rising
edge (Notes 2, 3)
Delay from JTCLK rising edge (Note 2)
18-1,
IL
= 0.8. The voltage threshold for all timing measurements is VDD/2. The
Figure
DESCRIPTION
18-2,
399
Figure
18-3,
Figure
18-5, and
MIN
20
10
10
0
0
0
0
0
0
0
0
0
0
TYP
Figure 18-6
MAX
10
30
30
30
30
30
30
30
30
30
5
apply to this
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns