DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 201

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For E3 LOS Assertion:
The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal
level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block.
(24dB below nominal in the “tolerance range” of G.775, where LOS may or may not be declared.)
For E3 LOS Clear:
The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a signal
level approximately 18dB below nominal, and enables data to come out of the CDR block. (18dB is in the
“tolerance range” of G.775, where LOS may or may not be declared.)
10.16.5.6 Receiver Power-Down
To minimize power consumption when the receiver is not being used, write a one to the PORT.CR1.PD bit. When
the receiver is powered down, the RCLKO pin is tri-stated. In addition, the RXP and RXN pins become high
impedance.
10.16.5.7 Receiver Jitter Tolerance
The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in
4-1. See
Figure 10-59. Receiver Jitter Tolerance
Figure
10-59.
10
1.0
0.1
DS3 GR-499 Cat II
DS3 GR-499 Cat I
10
15
30
STS-1 GR253
E3 G.823
100
10
5
300
1.5
FREQUENCY (Hz)
669
201
1k
2.3k
10k
DS318x JITTER TOLERANCE
22.3k
60k
100k
0.3
0.15
0.1
300k
800k
1M
Table