DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 224

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Not Used (—)
Bits 7 to 4: Port Interrupt Status Register Interrupt Enable [4:1] (PISRIE[4:1]) When any interrupt enable bit in
this group is enabled corresponding to a status bit set in the GL.ISR.PISR[4:1] status bit group, the INT pin will be
driven low.
Bit 1: Transmit System Interface Status Register Interrupt Status Interrupt Enable (TSSRIE). When this bit is
enabled, and the GL.ISR.TSSR status bit is set, the INT pin will be driven low.
Bit 0: Global Status Register Interrupt Status Interrupt Enable (GSRIE) When this interrupt enable bit is
enabled, and the GL.ISR.GSR status bit is set, the INT pin will be driven low.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 1: CLAD Loss of Lock (CLOL) – This bit is set when any of the PLLs in the CLAD are not locked to the
reference frequency.
Bit 0: Global Performance Monitoring Update Status (GPMS) This bit is set when all of the port performance
register update status bits (PORT.SR.PMS), that are enabled for global update control (PORT.CR1.PMUM=1), are
set. It is an “AND” of all the globally enabled port PMU status bits. In global software update mode, the global
update request bit (GL.CR1.PMU) should be held high until this status bit goes high.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = The associated update request signal is low or not all register updates are completed
1 = The requested performance register updates are all completed
PISRIE4
15
15
—
—
—
0
7
0
7
PISRIE3
14
14
—
—
—
0
6
0
6
GL.ISRIE
Global Interrupt Status Register Interrupt Enable
012h
GL.SR
Global Status Register
014h
PISRIE2
13
13
—
—
—
0
5
0
5
PISRIE1
12
12
—
—
—
0
0
4
4
224
11
11
—
—
—
—
0
3
0
3
10
10
—
—
—
—
0
2
0
2
TSSRIE
CLOL
—
—
9
0
1
0
9
1
GSRIE
GPMS
—
—
8
0
0
0
8
0