DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 20

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.13 Transmit PLCP Formatter Features
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3.14 Transmit DS3/E3 Formatter Features
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3.15 Transmit DS3/E3/STS-1 LIU Features
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3.16 Jitter Attenuator Features
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3.17 Clock Rate Adapter Features
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3.18 HDLC Overhead Controller Features
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Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes
Generation of BIP-8 (B1), FEBE and RAI (G1)
C1 cycle/stuff counter generation referenced to GPIO4 input pin, referenced to the received PLCP timing, or
based on an 8 kHz division of one of the clock sources
Automatic or manual insertion of FAS errors, BIP-8 errors
All path overhead fields can be sourced from the PLCP transmit overhead port
HDLC port for data link messages on F1, M1 or M2 bytes
Trail Trace port for trace messages on F1 byte
Insertion of framing overhead for M23 or C-bit parity DS3, or G.751 E3 or G.832 E3
B3ZS/HDB3 encoding
Generation of RDI, AIS, and DS3 idle signal
Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-bit errors,
M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)
HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or
two different code words back-to-back to send DS3 Line Loopback commands
16-byte Trail Trace Buffer port for the G.832 trail access point identifier
Insertion of G.832 payload type, and timing marker bits from registers
DS3 M23 C bits configurable as payload or overhead; as overhead they can be controlled from registers or the
transmit overhead port
Most framing overhead fields can be sourced from transmit overhead port
Formatter bypass mode for clear-channel or externally defined format applications
Support for subrate DS3/E3, internally or externally controlled (Fractional DS3/E3)
Wide 50+20% transmit clock duty cycle
Line Build-Out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor status indication
Fully integrated and requiring no external components
Can be placed in transmit or receive path
FIFO depth of 16 bits
Standard compliant transmission jitter and wander
Generation of the internally needed DS3 (44.736 MHz), E3 (34.368 MHz), and STS-1 (51.84 MHz) clocks a
from single input reference clock
Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz
Internally derived clocks can be used as references for LIU and jitter attenuator
Derived clocks can be transmitted off-chip for external system use
Standards compliant jitter and wander requirements.
Each port has a dedicated HDLC controller for DS3/E3 framer or PLCP link management
256-byte receive and transmit FIFOs
Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking, abort
generation/checking, flag generation/detection, and byte alignment
Programmable high and low water marks for the transmit and receive FIFOs
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