DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 59

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TMOD[1:0]
RADR[4:0]
RSCLK
TEOP
TERR
TSX
PIN
TYPE
I
I
I
I
I
I
TSPA goes low when the selected port is "full" or no port is selected. This signal is
updated on the rising edge of TSCLK.
In UTOPIA L3 mode this signal is low.
In POS-PHY L2 mode, this signal is driven when one of the ports is selected for data
transfer, and tri-state when TEN is deasserted, none of the ports is selected or when
data path reset is active.
POS-PHY L3 or UTOPIA L3 modes this signal is driven.
In UTOPIA L2 (reset default) mode this signal is tri-stated.
Transmit End Of Packet
TEOP: In POS-PHY L2 or L3 modes, this signal is used to indicate the last transfer
of a packet. This signal is sampled on the rising edge of TSCLK.
In UTOPIA L2 or L3 modes, this signal is ignored.
Transmit Start Of Transfer
TSX: In POS-PHY L3 mode, this signal indicates the start of a data transfer. TSX
goes high goes high immediately before the start of data transfer to indicate that the
in-band port address is present on TDATA. TSX goes high when the value of TDATA
is the address of the transmit port to which data is to be transferred. When TSX goes
low, all subsequent transfers will be to the port specified by the in-band address.
This signal is sampled on the rising edge of TSCLK. TSX is only valid when TEN is
high.
In UTOPIA L2, UTOPIA L3 or POS-PHY L2 modes, this signal is ignored.
Transmit Packet Data Modulus [1:0]
TMOD[1:0]: In POS-PHY L2 or L3 modes, this signal indicates the number of valid
bytes on the TDATA bus.
This signal is sampled on the rising edge of TSCLK. TMOD is only valid when TEOP
is high.
In 16-bit POS-PHY L2 or 16-bit POS-PHY L3 mode, TMOD[1] is ignored.
In 8-bit POS-PHY L2 or 8-bit POS-PHY L3 modes, TMOD[1:0] are ignored.
In UTOPIA L2 or UTOPIA L3 modes, TMOD[1:0] are ignored.
Transmit Packet Error
TERR: In POS-PHY L2 or POS-PHY L3 modes, this signal indicates that the current
packet is erred. When TERR is high, the current packet should be aborted. This
signal is sampled on the rising edge of TSCLK. TERR is only valid when TEOP is
high.
In UTOPIA L2 or UTOPIA L3 modes, this signal is ignored.
Receive System Clock
RSCLK: This signal is used to sample or update the other receive system interface
signals.
RSCLK has a maximum frequency of 66 MHz in UTOPIA L3 or POS-PHY L3 modes
and 52 MHZ in UTOPIA L2 or POS-PHY L2 modes.
Receive Address [4:0]
RADR[4:0]: In UTOPIA L2, Utopia L3 or POS-PHY L2 modes, this 5-bit address bus
is used by the ATM/Link layer device to select a specific port for data transfer and
polling FIFO status. RADR[4] is the MSB and RADR[0] is the LSB. This bus is
sampled on the rising edge of RSCLK. In POS-PHY Level 3 (or SPI-3) mode, this bus
is ignored.
TMOD[1:0]=00
TMOD[1:0]=01
TMOD[1:0]=10
TMOD[1:0]=11
59
TDAT[31:0] valid
TDAT[31:8] valid
TDAT[31:16] valid
TDAT[31:24] valid
FUNCTION