DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 366

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Receive Packet Count (RPC[15:0]) – Lower 16 bits of 24 bits. Register description follows next
register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Receive Packet Count (RPC[23:16]) - Upper 8 bits of Register.
Receive Packet Count (RPC[23:0]) – These 24 bits indicate the number of packets stored in the receive FIFO
without an abort indication. Note: Packets discarded due to system loopback or an overflow condition will be
included in this count. This register is updated via the PMU signal (see Section 10.4.5).
RPC15
RPC23
RPC7
15
15
—
0
7
0
0
7
0
RPC14
RPC22
RPC6
14
14
—
0
6
0
0
6
0
PP.RPCR1
Packet Processor Receive Packet Count Register 1
(1,3,5,7)D4h
PP.RPCR2
Packet Processor Receive Packet Count Register 2
(1,3,5,7)D6h
RPC13
RPC21
RPC5
13
13
—
0
5
0
0
5
0
RPC12
RPC20
RPC4
12
12
—
0
0
0
0
4
4
366
RPC11
RPC19
RPC3
11
11
—
0
3
0
0
3
0
RPC10
RPC18
RPC2
10
10
—
0
2
0
0
2
0
RPC17
RPC9
RPC1
—
9
0
1
0
9
0
1
0
RPC16
RPC8
RPC0
—
8
0
0
0
8
0
0
0