DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 22

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DS3184DK

Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3184DK

Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.25 Test Features
Subrate algorithm selection is on per-port basis
Internal subrate mechanism allows down to bit-level granularity of the DS3 or E3 payload
Five pin JTAG port
All functional pins are in/out pins in JTAG mode
Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
RAM BIST on all internal RAM
High-Z pin to force all digital output and in/out pins into HIZ
TEST pin for manufacturing scan test modes
(FFRAC) Externally controlled with DS3 or E3 payload manipulating capability
(XFRAC) Externally controlled with flexible DS3 or E3 data rate reduction capability
(IFRAC) Internally controlled with simple DS3 or E3 data rate reduction capability
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