DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 31
DS3184DK
Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3184DK.pdf
(400 pages)
Specifications of DS3184DK
Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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6.6 DS3/E3 G.751 PLCP ATM Mode
DS3/E3 G.751 PLCP ATM mode is a normal mode of operation for the DS318x devices, which maps/demaps ATM
cells into/from the DS3/E3 PLCP data stream. Major functional blocks for the DS3/E3 ATM/Packet mode are shown
in
The PMCPE configuration bit is ignored when in PLCP mode and ATM cell processing is forced.
Table 6-6. DS3/E3 G.751 PLCP ATM Mode Configuration Registers
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-6. DS3/E3 G.751 PLCP ATM Mode
TOHMOn/
Figure
RLCLKn
RNEGn/
ROHMIn
TLCLKn
RPOSn/
TPOSn/
TNEGn/
RLCVn/
RDATn
TDATn
RXPn
RXNn
TXPn
TXNn
MODE
6-6. Mapping configuration is programmable on per-port basis and is shown in
Clock Rate
DS3/E3
Receive
Transmit
DS3/E3
Adapter
LIU
LIU
FM[5:0]
0XX100
0XX100
0XX100
0XX100
0XX100
0XX100
Decoder
Encoder
B3ZS/
HDB3
HDB3
B3ZS/
TUA1
TAIS
SIM[1:0]
GL.CR1
IEEE 1149.1
00
01
10
11
10
11
Access Port
JTAG Test
DS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
FEAC
PORT.CR2
HDLC
PMCPE
31
X
X
1
1
0
0
GEN
UA1
PLCP
TX
TRACE
TRAIL
RX PLCP
Processor
Processor
BERT
BERT
Rx Cell
Tx Cell
TX
RX
Microprocessor
Interface
Table
6-6.
FIFO
FIFO
Rx
Tx
Interface
System
n = port # (1-4)
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