DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 299

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 5: Transmit Payload Type (TPT[2:0]) – These bits determines the value transmitted in the payload type
(third, fourth, and fifth bits in the MA byte).
Bit 4: Transmit Timing Source Indicator Bit Generation Disable (TTIGD) – When 0, the last three bits of the MA
byte (MA[6:8]) are generated from the four timing source indicator bits TTI[3:0]. When 1, TTI[3] is ignored and
TTI[2:0] are directly inserted into the last three bits of the MA byte.
Bits 3 to 0: Transmit Timing Source Indication (TTI[3:0]) – These four bits make up the timing source indicator
bits.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 8: Transmit GC Byte (TGC[7:0]) – These eight bits are the GC byte to be inserted into the E3 frame.
Bits 7 to 0: Transmit NR Byte (TNR[7:0]) – These eight bits are the NR byte to be inserted into the E3 frame.
TGC7
TNR7
TPT2
15
15
—
0
7
0
0
7
0
TGC6
TNR6
TPT1
14
14
—
0
6
0
0
6
0
E3G832.TMABR
E3 G.832 Transmit MA Byte Register
(1,3,5,7)1Ch
E3G832.TNGBR
E3 G.832 Transmit NR and GC Byte Register
(1,3,5,7)1Eh
TGC5
TNR5
TPT0
13
13
—
0
5
0
0
5
0
TTIGD
TGC4
TNR4
12
12
—
0
0
0
0
4
4
299
TGC3
TNR3
TTI3
11
11
—
0
3
0
0
3
0
TGC2
TNR2
TTI2
10
10
—
0
2
0
0
2
0
TGC1
TNR1
TTI1
—
9
0
1
0
9
0
1
0
TGC0
TNR0
TTI0
—
8
0
0
0
8
0
0
0