DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 112

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10-12. Global 8 kHz Reference Source Table
Table 10-13
Table 10-13. Port 8 kHz Reference Source Table
The 8 kHz reference logic tree is shown below.
Figure 10-7. 8KREF Logic
GL.CR2.
PORT.CR3.P8KRS[1:0]
G8KIS
0
0
0
0
0
0
0
0
1
FROM CLAD
PORT.CR3.P8KRS[0]
0X
10
11
lists the selectable sources for port 8 kHz reference sources.
G8KRS[2:0]
GL.CR2.
RX PLCP 8KREF
XXX
000
001
010
011
100
101
110
111
FRAME MODE
RX CLOCK
G8KRS[1:0]
TX CLOCK
(FM BITS)
CC52 CLK
DS3 CLK
GL.CR2.
E3 CLK
GPIO4
GL.CR2.G8KRS[1:0]
Receive PLCP 8kHZ output
Receive internal framer clock (based on RLCLKn
pin or RX LIU recovered clock)
Transmit internal framer clock (based on TCLKIn
pin or CLAD clock)
None, the 8KHZ divider is disabled.
Derived from CLAD DS3 clock output or CLKA pin if CLAD
is disabled (Note: CLAD is disabled after reset)
Derived from CLAD E3 clock output or CLKB pin if CLAD is
disabled
Derived from CLAD STS-1 clock output or CLKC pin if CLAD
is disabled
Port 1 8KREF source selected by P8KRS[1:0]
Port 2 8KREF source selected by P8KRS[1:0]
Port 3 8KREF source selected by P8KRS[1:0]
Port 4 8KREF source selected by P8KRS[1:0]
GPIO4 pin
0
1
1
2
3
CLOCK DIVIDER
OTHER
8KREF
PORT
CLOCK DIVIDER
PORT.CR3.
SOURCE
P8KRS[1]
0
1
2
3
SOURCE
112
0
1
GL.CR2.G8KRS[2]
0
1
0
1
G8KREF
0
1
PORT.CR3.P8KREF
GLOBAL 8KREF
TX PLCP 8KREF
PORT 8KREF