DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 310

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.10.8 Receive Clear Channel
The receive clear-channel mode uses four registers.
12.10.8.1 Register Map
Table 12-40. Receive Clear-Channel Register Map
12.10.8.2 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of a LOS condition will cause
downstream AIS to be inserted. When 1, the presence of a LOS condition will not cause downstream AIS to be
inserted.
(1,3,5,7)2Ch
(1,3,5,7)3Ch
(1,3,5,7)2Ah
(1,3,5,7)2Eh
(1,3,5,7)3Ah
(1,3,5,7)3Eh
(1,3,5,7)20h
(1,3,5,7)22h
(1,3,5,7)24h
(1,3,5,7)26h
(1,3,5,7)28h
(1,3,5,7)30h
(1,3,5,7)32h
(1,3,5,7)34h
(1,3,5,7)36h
(1,3,5,7)38h
ADDRESS
Reserved
Reserved
15
0
7
0
CC.RSRIE1
REGISTER
CC.RSRL1
CC.RSR1
CC.RCR
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
Reserved
14
0
6
0
Clear-Channel Receive Control Register
Reserved
Clear-Channel Receive Status Register 1
Reserved
Clear-Channel Receive Status Register Latched 1
Reserved
Clear-Channel Receive Status Register Interrupt Enable 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Unused
Unused
CC.RCR
Clear-Channel Receive Control Register
(1,3,5,7)20h
Reserved
Reserved
13
0
5
0
REGISTER DESCRIPTION
Reserved
MDAISI
12
0
0
4
310
Reserved
AAISD
11
0
3
0
Reserved
Reserved
10
0
2
0
Reserved
Reserved
9
0
1
0
Reserved
Reserved
8
0
0
0