DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 230

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 13 to 8: Receive Maximum Burst Length (RMBL[5:0]) – In POS-PHY Level 3, these six bits limit the
maximum number of four byte data groups that can be transferred from a port before switching to another port. The
maximum number of transfers is RMBL[5:0]+1 in 32-bit mode, 2 x (RMBL[5:0]+1} in 16-bit mode, and
4*(RMBL[5:0]+1} in 8-bit mode. Note: if no other port is ready to start a transfer, transfer from the current port will
continue if the port contains more data than the almost empty level or contains an end of packet. These bits are
ignored in POS-PHY Level 2 or UTOPIA mode. A value of 00h disables the maximum burst length. In 32-bit mode,
a value of 01h is treated as 02h.
Bits 7 to 0: Receive System Loopback Bandwidth Limit (RLBL[7:0]) – These eight bits limit the maximum
bandwidth of a single port during system loopback. For RLBL[7:0] equals x, the bandwidth will be limited to 1/x of
the maximum system interface bandwidth. In 8-bit and 16-bit mode, a value of 00h is treated as 01h. In 32-bit
mode, a value of 01h or 00h is treated as 02h.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 0: Receive System Interface Clock Active Latched (RSCLKAL) – This bit is set when RSCLK is active.
RLBL7
15
15
—
—
—
0
7
0
7
RLBL6
14
14
—
—
—
0
6
0
6
SI.RCR2
System Interface Receive Control Register 2
03Ah
SI.RSRL
System Interface Receive Status Register Latched
03Ch
RMBL5
RLBL5
13
13
—
—
0
5
0
5
RMBL4
RLBL4
12
12
—
—
0
0
4
4
230
RMBL3
RLBL3
11
11
—
—
0
3
0
3
RMBL2
RLBL2
10
10
—
—
0
2
0
2
RMBL1
RLBL1
—
—
9
0
1
0
9
1
RSCLKAL
RMBL0
RLBL0
—
8
0
0
0
8
0