DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 34

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.8 Clear-Channel ATM/Packet Mode
The Clear-Channel ATM/Packet Mode maps/demaps ATM cells or HDLC packets into/from a serial datastream,
bypassing the DS3/E3 formatter/framer. Major functional blocks for the Clear-Channel ATM/Packet Mode are
shown in
Table 6-8. Clear-Channel ATM/Packet Mode Configuration Modes
UTOPIA L2 ATM
UTOPIA L3 ATM
POS-PHY L2 ATM
POS-PHY L3 ATM
POS-PHY L2 Packet
POS-PHY L3 Packet
Figure 6-8. Clear-Channel ATM/Packet Modes
TOHMOn/
RLCLKn
RNEGn/
ROHMIn
RPOSn/
TLCLKn
TPOSn/
TNEGn/
RLCVn/
RDATn
TDATn
RXNn
RXPn
TXPn
TXNn
MODE
Figure
Clock Rate
Receive
DS3/E3
Transmit
DS3/E3
Adapter
LIU
LIU
6-8. Mapping configuration is programmable on per-port basis and is shown in
1XX0X0
1XX0X0
1XX0X0
1XX0X0
1XX0X0
1XX0X0
FM[5:0]
Decoder
Encoder
HDB3
B3ZS/
B3ZS/
HDB3
TUA1
TAIS
SIM[1:0]
GL.CR1
IEEE P1149.1
00
01
10
11
10
11
JTAG Test
Access Port
PORT.CR2
PMCPE
34
X
X
1
1
0
0
GEN
UA1
Rx Packet
Processor
Processor
RX BERT
Processor
Processor
TX BERT
Tx Packet
Rx Cell
Tx Cell
Microprocessor
Interface
FIFO
Table
FIFO
Tx
Rx
n = port # (1-4)
6-8.