NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 540

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Device identification register, 6-11
DMA
Documentation, xlii
DSCLK, 5-2
E
Electrical specifications
Ethernet
Index-2
module enhancements, 2-4
real-time support, 5-34
taken branch, 5-4
theory, 5-34
address modes, 10-2
byte count register, 10-6
controller registers, 10-2
data transfer types, 10-1
destination address register, 10-6
interrupt register, 10-4
mode register, 10-2
source address register, 10-5
AC, 23-5
AC timing
clock input and output timing, 23-5
DC, 23-3
DL and GCI interface timing, 23-20
maximum ratings, 23-1
MII async inputs signal timing, 23-17
operating temperature, 23-2
output loading, 23-3
processor bus input timing, 23-6
QSPI, 23-27, 23-28
SDRAM interface timing, 23-13
supply, input voltage, and storage temperature, 23-1
thermal resistance, 23-2
timer module AC timing, 23-18
USART module AC timing, 23-19
address recognition, 11-7
buffer descriptors
CAM interface, 11-7
collision handling, 11-9
control register, 11-12
descriptor active register, 11-15
descriptor ring register
error handling, 11-9
FEC initialization, 11-31
debug, 23-12
fast Ethernet, 23-15
GPIO port, 23-25
IEEE 1149.1 (JTAG), 23-26
USB interface, 23-25
receive, 11-33
transmit, 11-34
pointer-to-receive, 11-28
pointer-to-transmit, 11-28
MCF5272 User’s Manual
INDEX
Exception processing
Exceptions
Execution timings
External bus interface overview, 1-5
F
Fault-on-fault halt, 5-15
Features overview, 1-1
Frame reception, 11-5
FIFO
frame
hardware initialization, 11-30
hash table
initialization sequence, 11-30
internal and external loopback, 11-9
interpacket gap time, 11-9
interrupt
loopbacks, 11-9
maximum frame length register, 11-23
MII
module operation, 11-2
programming model, 11-11
RAM perfect match address register
receive buffer size register, 11-29
receive control register, 11-22
transceiver connection, 11-3
transmit
user initialization, 11-30
overview, 2-26
processor exceptions, 2-29
stack frame definition, 2-28
bus, 20-4
miscellaneous, 2-24
one operand, 2-22
two operands, 2-23
receive bound register, 11-19
receive start register, 11-20
transmit start register, 11-22
reception, 11-5
transmission, 11-4
algorithm, 11-8
high register, 11-27
low register, 11-27
event register, 11-12
mask register, 11-13
vector status register, 11-14
management frame register, 11-17
speed control register, 11-18
high, 11-26
low, 11-25
control register, 11-24
descriptor active register, 11-16
FIFO watermark, 11-21
MOTOROLA