NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet
NNDK-MOD5272-KIT
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NNDK-MOD5272-KIT Summary of contents
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MCF5272 ColdFire Microprocessor User’s Manual MCF5272UM/D 3/2002 REV 2 Integrated ® ...
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the ...
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Hardware Multiply/Accumulate (MAC) Unit System Integration Module (SIM) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Pulse-Width Modulation (PWM) Module IEEE 1149.1 Test Access Port (JTAG) Appendix A: List of Memory Maps Appendix B: Buffering and Impedence ...
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Overview 1 ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 System Integration Module (SIM) 6 Interrupt Controller 7 Chip-Select Module 8 SDRAM Controller 9 DMA Controller Module 10 Ethernet Module 11 Universal Serial Bus ...
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Paragraph Number 1.1 MCF5272 Key Features...................................................................................... 1-1 1.2 MCF5272 Architecture ....................................................................................... 1-4 1.2.1 Version 2 ColdFire Core................................................................................. 1-4 1.2.2 System Integration Module (SIM).................................................................. 1-5 1.2.2.1 External Bus Interface ................................................................................ 1-5 1.2.2.2 Chip Select and Wait State Generation ...................................................... 1-5 1.2.2.3 ...
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Paragraph Number 2.2 Programming Model ........................................................................................... 2-5 2.2.1 User Programming Model .............................................................................. 2-6 2.2.1.1 Data Registers (D0–D7) ............................................................................. 2-6 2.2.1.2 Address Registers (A0–A6) ........................................................................ 2-6 2.2.1.3 Stack Pointer (A7, SP) ................................................................................ 2-7 2.2.1.4 Program Counter (PC) ................................................................................ 2-7 2.2.1.5 Condition ...
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Paragraph Number 4.1 Interactions between Local Memory Modules ................................................... 4-1 4.2 Local Memory Registers..................................................................................... 4-2 4.3 SRAM Overview ................................................................................................ 4-2 4.3.1 SRAM Operation ............................................................................................ 4-2 4.3.2 SRAM Programming Model........................................................................... 4-2 4.3.2.1 SRAM Base Address Register (RAMBAR)............................................... 4-3 4.3.2.2 SRAM Initialization.................................................................................... ...
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Paragraph Number 5.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-11 5.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-12 5.4.7 Trigger Definition Register (TDR) ............................................................... 5-13 5.5 Background Debug Mode (BDM) .................................................................... 5-15 5.5.1 CPU Halt....................................................................................................... 5-15 5.5.2 BDM Serial Interface.................................................................................... 5-16 ...
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Paragraph Number 6.2.4 System Protection Register (SPR) .................................................................. 6-6 6.2.5 Power Management Register (PMR).............................................................. 6-7 6.2.6 Activate Low-Power Register (ALPR)......................................................... 6-10 6.2.7 Device Identification Register (DIR)............................................................ 6-11 6.2.8 Software Watchdog Timer............................................................................ 6-12 6.2.8.1 Watchdog Reset Reference Register (WRRR) ......................................... 6-13 ...
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Paragraph Number 9.3 Interface to SDRAM Devices ............................................................................. 9-4 9.4 SDRAM Banks, Page Hits, and Page Misses ..................................................... 9-6 9.5 SDRAM Registers .............................................................................................. 9-6 9.5.1 SDRAM Configuration Register (SDCR) ...................................................... 9-6 9.5.2 SDRAM Timing Register (SDTR) ................................................................. 9-8 9.6 Auto ...
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Paragraph Number 11.4.8.1 Transmission Errors................................................................................ 11-10 11.4.8.2 Reception Errors ..................................................................................... 11-10 11.5 Programming Model ....................................................................................... 11-11 11.5.1 Ethernet Control Register (ECR)................................................................ 11-12 11.5.2 Interrupt Event Register (EIR).................................................................... 11-12 11.5.3 Interrupt Mask Register (EIMR)................................................................. 11-13 11.5.4 Interrupt Vector Status Register (IVSR)..................................................... ...
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Paragraph Number 12.2.1.1 USB Transceiver Interface ....................................................................... 12-4 12.2.1.2 Clock Generator........................................................................................ 12-4 12.2.1.3 USB Control Logic ................................................................................... 12-4 12.2.1.4 Endpoint Controllers................................................................................. 12-5 12.2.1.5 USB Request Processor ............................................................................ 12-5 12.3 Register Description and Programming Model ................................................ 12-7 12.3.1 USB Memory Map........................................................................................ ...
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Paragraph Number 12.4.4.2 Isochronous Endpoints............................................................................ 12-31 12.4.4.2.1 IN Endpoints....................................................................................... 12-32 12.4.4.2.2 OUT Endpoints................................................................................... 12-32 12.4.5 Class- and Vendor-Specific Request Operation ......................................... 12-32 12.4.6 remote wakeup and resume Operation........................................................ 12-33 12.4.7 Endpoint Halt Feature................................................................................. 12-33 12.5 Line Interface .................................................................................................. 12-34 12.5.1 ...
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Paragraph Number 13.5.5 B2 Data Transmit Registers (P0B2TR–P3B2TR) ...................................... 13-17 13.5.6 D Data Transmit Registers (P0DTR–P3DTR)............................................ 13-18 13.5.7 Port Configuration Registers (P0CR–P3CR).............................................. 13-19 13.5.8 Loopback Control Register (PLCR) ........................................................... 13-20 13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR).................................... 13-21 13.5.10 Periodic Status Registers ...
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Paragraph Number 14.4.4 Transfer Length............................................................................................. 14-8 14.4.5 Data Transfer ................................................................................................ 14-8 14.5 Programming Model ......................................................................................... 14-9 14.5.1 QSPI Mode Register (QMR) ........................................................................ 14-9 14.5.2 QSPI Delay Register (QDLYR) ................................................................. 14-11 14.5.3 QSPI Wrap Register (QWR)....................................................................... 14-12 14.5.4 QSPI Interrupt Register ...
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Paragraph Number 16.3.13 UART Transmitter FIFO Registers (UTFn) ............................................... 16-15 16.3.14 UART Receiver FIFO Registers (URFn) ................................................... 16-16 16.3.15 UART Fractional Precision Divider Control Registers (UFPDn) .............. 16-17 16.3.16 UART Input Port Registers (UIPn) ............................................................ 16-18 16.3.17 UART Output Port ...
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Paragraph Number 17.3.3 Port C Data Direction Register (PCDDR) .................................................. 17-11 17.4 Port Data Registers ......................................................................................... 17-11 17.4.1 Port Data Register (PxDAT)....................................................................... 17-11 Pulse Width Modulation (PWM) Module 18.1 Overview........................................................................................................... 18-1 18.2 PWM Operation ................................................................................................ 18-2 18.3 PWM Programming Model............................................................................... ...
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Paragraph Number 19.9 General-Purpose I/O (GPIO) Ports ................................................................. 19-23 19.10 UART0 Module Signals and PB[4:0] ............................................................. 19-24 19.10.1 Transmit Serial Data Output (URT0_TxD/PB0) ........................................ 19-24 19.10.2 Receive Serial Data Input (URT0_RxD/PB1) ............................................ 19-24 19.10.3 Clear-to-Send (URT0_CTS/PB2) ............................................................... 19-24 19.10.4 Request ...
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Paragraph Number 19.15.4 Synchronous Peripheral Chip Select 0 (QSPI_CS0/BUSW0).................... 19-30 19.15.5 Synchronous Peripheral Chip Select 1 (QSPI_CS1/PA11) ........................ 19-31 19.15.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) .............. 19-31 19.15.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3)............ 19-31 19.16 Physical Layer Interface ...
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Paragraph Number 20.1 Features ............................................................................................................. 20-1 20.2 Bus and Control Signals.................................................................................... 20-1 20.2.1 Address Bus (A[22:0]).................................................................................. 20-2 20.2.2 Data Bus (D[31:0]) ....................................................................................... 20-2 20.2.3 Read/Write (R/W)......................................................................................... 20-2 20.2.4 Transfer Acknowledge (TA)......................................................................... 20-3 20.2.5 Transfer Error Acknowledge (TEA)............................................................. 20-3 20.3 Bus ...
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Paragraph Number 22.1 Pinout ................................................................................................................ 22-1 22.2 Package Dimensions ......................................................................................... 22-2 23.1 Maximum Ratings............................................................................................. 23-1 23.1.1 Supply, Input Voltage, and Storage Temperature......................................... 23-1 23.1.2 Operating Temperature ................................................................................. 23-2 23.1.3 Resistance ..................................................................................................... 23-2 23.2 DC Electrical Specifications ............................................................................. 23-3 23.2.1 Output ...
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Paragraph Number Buffering and Impedance Matching xxii CONTENTS Title Appendix B Index MCF5272 User’s Manual Page Number MOTOROLA ...
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Figure Number 1-1 MCF5272 Block Diagram............................................................................................. 1-2 2-1 ColdFire Pipeline .......................................................................................................... 2-2 2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-4 2-3 ColdFire Programming Model...................................................................................... 2-6 2-4 Condition Code Register (CCR) ................................................................................... 2-7 2-5 Status Register (SR)...................................................................................................... 2-9 2-6 Vector Base Register ...
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Figure Number 5-20 / Command Sequence .......................................................................... 5-23 WAREG WDREG 5-19 / Command Format.............................................................................. 5-23 WAREG WDREG 5-22 Command Sequence.......................................................................................... 5-24 READ 5-21 Command/Result Formats................................................................................. 5-24 READ 5-23 Command Format ............................................................................................ 5-25 WRITE 5-24 Command Sequence ........................................................................................ 5-26 WRITE 5-25 ...
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Figure Number 8-1 Chip Select Base Registers (CSBRn) ........................................................................... 8-3 8-2 Chip Select Option Registers (CSORn)....................................................................... 8-5 9-1 SDRAM Controller Signals .......................................................................................... 9-2 9-2 54-Pin TSOP SDRAM Pin Definition .......................................................................... 9-3 9-3 SDRAM Configuration Register (SDCR) .................................................................... 9-6 9-4 SDRAM ...
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Figure Number 11-22 Hash Table Low (HTLR)......................................................................................... 11-27 11-23 Pointer to Receive Descriptor Ring (ERDSR).......................................................... 11-28 11-24 Pointer to Transmit Descriptor Ring (ETDSR) ........................................................ 11-29 11-25 Receive Buffer Size (EMRBR)................................................................................. 11-29 11-26 Receive Buffer Descriptor (RxBD) .......................................................................... 11-33 11-27 Transmit ...
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Figure Number 13-12 PLIC Clock Generator .............................................................................................. 13-13 13-13 B1 Receive Data Registers P0B1RR–P3B1RR ........................................................ 13-16 13-14 B2 Receive Data Registers P0B2RR – P3B2RR ...................................................... 13-16 13-15 D Receive Data Registers P0DRR–P3DRR ............................................................. 13-17 13-16 B1 Transmit Data Registers P0B1TR–P3B1TR ...
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Figure Number 15-3 Timer Reference Registers (TRR0–TRR3) ................................................................ 15-4 15-4 Timer Capture Registers (TCAP0–TCAP3) ............................................................... 15-5 15-5 Timer Counter (TCN0–TCN3) ................................................................................... 15-5 15-6 Timer Event Registers (TER0–TER3)........................................................................ 15-5 16-1 Simplified Block Diagram .......................................................................................... 16-1 16-2 UART Mode Registers 1 (UMR1n)............................................................................ ...
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Figure Number 18-2 PWM Control Registers (PWCRn)............................................................................. 18-3 18-3 PWM Width Register (PWWDn) ............................................................................... 18-4 18-4 PWM Waveform Examples (PWCRn[EN] = 1)......................................................... 18-5 19-1 MCF5272 Block Diagram with Signal Interfaces ...................................................... 19-2 20-1 Internal Operand Representation ................................................................................ 20-5 20-2 MCF5272 ...
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Figure Number 23-4 SRAM Bus Cycle Terminated by TA....................................................................... 23-10 23-5 SRAM Bus Cycle Terminated by TEA .................................................................... 23-11 23-6 Reset and Mode Select/HIZ Configuration Timing.................................................. 23-11 23-7 Real-Time Trace AC Timing .................................................................................... 23-12 23-8 BDM Serial Port AC Timing ...
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Table Number 2-1 CCR Field Descriptions ............................................................................................... 2-7 2-2 MOVEC Register Map ................................................................................................. 2-8 2-3 Status Field Descriptions .............................................................................................. 2-9 2-4 Integer Data Formats................................................................................................... 2-10 2-5 ColdFire Effective Addressing Modes....................................................................... 2-13 2-6 Notational Conventions ............................................................................................. 2-14 2-7 User-Mode Instruction Set ...
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Table Number 5-6 ABLR Field Description ............................................................................................... 5-9 5-7 ABHR Field Description............................................................................................... 5-9 5-8 CSR Field Descriptions............................................................................................... 5-10 5-9 DBR Field Descriptions.............................................................................................. 5-12 5-10 DBMR Field Descriptions .......................................................................................... 5-12 5-11 Access Size and Operand Data Location .................................................................... 5-12 5-12 PBR ...
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Table Number 9-2 Connecting BS[3:0] to DQMx ...................................................................................... 9-4 9-3 Configurations for 16-Bit Data Bus.............................................................................. 9-4 9-4 Configurations for 32-Bit Data Bus.............................................................................. 9-4 9-5 Internal Address Multiplexing (16-Bit Data Bus) ........................................................ 9-5 9-6 Internal Address Multiplexing (32-Bit Data Bus) ........................................................ ...
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Table Number 11-27 ERDSR Field Descriptions ....................................................................................... 11-28 11-28 ETDSR Field Descriptions ....................................................................................... 11-29 11-29 EMRBR Field Descriptions ...................................................................................... 11-30 11-30 Hardware Initialization ............................................................................................. 11-30 11-31 ETHER_EN = 0 ........................................................................................................ 11-30 11-32 User Initialization Process (before ETHER_EN) ..................................................... 11-31 11-33 ...
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Table Number 13-15 PDRQR Field Descriptions....................................................................................... 13-31 13-16 P0SDR–P3SDR Field Descriptions .......................................................................... 13-32 13-17 PCSR Field Descriptions .......................................................................................... 13-33 14-1 QSPI Input and Output Signals and Functions ........................................................... 14-3 14-2 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate ...
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Table Number 19-3 Byte Strobe Operation for 32-Bit Data Bus.............................................................. 19-20 19-4 Byte Strobe Operation for 16-Bit Data Bus—SRAM Cycles.................................. 19-20 19-5 Byte Strobe Operation for 16-Bit Data Bus—SDRAM Cycles............................... 19-20 19-6 Connecting BS[3:0] to DQMx .................................................................................. 19-21 19-7 Processor ...
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Table Number A-2 CPU Space Registers Memory Map ............................................................................ A-2 A-3 On-Chip Peripherals and Configuration Registers Memory Map ............................... A-2 A-4 Interrupt Control Register Memory Map..................................................................... A-2 A-5 Chip Select Register Memory Map.............................................................................. A-3 A-6 GPIO Port Register Memory Map ...
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Table Number xxxviii TABLES Title MCF5272 User’s Manual Page Number MOTOROLA ...
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About This Book The primary objective of this user’s manual is to define the functionality of the MCF5272 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in ...
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Organization — Section 4.3, “SRAM Overview,” describes the MCF5272 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM. — Section 4.4, ...
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The USB Specification, Revision 1 recommended supplement to this chapter. It can be downloaded from http://www.usb.org. Chapter 2 of this specification, Terms and Abbreviations, provides definitions of many of the words found here. • Chapter 13, “Physical Layer ...
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Suggested Reading • Chapter 21, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the MCF5272 Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE 1149.1 standard and provides additional information specific to ...
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ColdFire MCF5206E User’s Manual (MCF5206EUM/AD) — ColdFire MCF5307 User’s Manual (MCF5307UM/AD) — ColdFire MCF5407 User’s Manual (MCF5407UM/AD) • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. ...
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Acronyms and Abbreviations Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document. Table i. Acronyms and Abbreviated Terms Term ADC Analog-to-digital conversion ALU Arithmetic logic unit AVEC Autovector BDM Background debug mode BIST Built-in self test ...
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Table i. Acronyms and Abbreviated Terms (Continued) Term PLIC Physical layer interface controller PLL Phase-locked loop PLRU Pseudo least recently used POR Power-on reset PQFP Plastic quad flat pack PWM Pulse width modulation QSPI Queued serial peripheral interface RISC Reduced ...
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Terminology Conventions Table ii. Notational Conventions (Continued) Instruction ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register DDATA Debug data port PST Processor ...
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Table ii. Notational Conventions (Continued) Instruction / Arithmetic division ~ Invert; operand is logically complemented & Logical AND | Logical OR ^ Logical exclusive OR << Shift left (example: D0 << shift D0 left 3 bits) >> Shift ...
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Terminology Conventions Register Identifiers Register identifiers in this user’s manual were changed from names used in early versions of the manual released under non-disclosure agreement (NDA). Because a significant amount of collateral documentation, such as source code, was developed using ...
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Table v. Chip Select Register Memory Map (Continued) MBAR Register Name Offset 0x0054 CS Option Register 2 0x0058 CS Base Register 3 0x005C CS Option Register 3 0x0060 CS Base Register 4 0x0064 CS Option Register 4 0x0068 CS Base ...
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Terminology Conventions Table viii. PWM Module Memory Map MBAR Register Name Offset 0x00C0 PWM Control Register 0 0x00C4 PWM Control Register 1 0x00C8 PWM Control Register 2 0x00D0 PWM Pulse Width Register 0 0x00D4 PWM Pulse Width Register 1 0x00D8 ...
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Table x. UART0 Module Memory Map (Continued) MBAR Register Name Offset 0x0134 UART0 CTS Unlatched Input 0x0138 UART0 RTS O/P Bit Set Command Register 0x013C UART0 RTS O/P Bit Reset Command Register Table xi. UART1 Module Memory Map MBAR Register ...
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Terminology Conventions Table xiii. Timer Module Memory Map MBAR Register Name Offset 0x0200 Timer 0 Mode Register 0x0204 Timer 0 Reference Register 0x0208 Timer 0 Capture Register 0x020C Timer 0 Counter Register 0x0210 Timer 0 Event Register 0x0220 Timer 1 ...
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Table xiv. PLIC Module Memory Map (Continued) MBAR Register Name Offset 0x031C Port3 B2 Data Receive 0x0320 Port0-3 D Data Receive 0x0328 Port0 B1 Data Transmit 0x032C Port1 B1 Data Transmit 0x0330 Port2 B1 Data Transmit 0x0334 Port3 B1 Data ...
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Terminology Conventions Table xiv. PLIC Module Memory Map (Continued) MBAR Register Name Offset 0x037C GCI C/I TX Status 0x0384 Port0-1 Periodic Status 0x0388 Port2-3 Periodic Status 0x038C Aperiodic Interrupt Status Register; Loop back Control 0x0392 D Channel Request 0x0394 Port0-1 ...
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Table xv. Ethernet Module Memory Map (Continued) MBAR Register Name Offset 0x0C14 Ethernet Tx Descriptor Rin 0x0C18 Ethernet Rx Buffer Size 0x0C40 FIFO RAM – 0x0DFF Table xvi. USB Module Memory Map MBAR Register Name Offset 0x1002 USB Frame Number ...
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Terminology Conventions Table xvi. USB Module Memory Map (Continued) MBAR Register Name Offset 0x106C USB General/Endpoint 0 Interrupt Status Register 0x1072 USB Endpoint 1 Interrupt Status Register 0x1076 USB Endpoint 2 Interrupt Status Register 0x107A USB Endpoint 3 Interrupt Status ...
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The MBAR Offset column corresponds to the tables found in Appendix A, “List of Memory Maps.” 16- and/or 8-bit wide registers may be offset bytes from the offset address shown above. Refer to the ...
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Terminology Conventions lviii MCF5272 User’s Manual MOTOROLA ...
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Chapter 1 Overview This chapter provides an overview of the MCF5272 microprocessor features, including the major functional components. 1.1 MCF5272 Key Features A block diagram of the MCF5272 is shown in Figure 1-1. The main features are as follows: • ...
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MCF5272 Key Features JTAG Local Memory Instruction SYSTEM INTEGRATION MODULE (SIM) System Control Base Address SCR PMR WRRR WCR SPR ALPR WIRR WER SDRAM Controller Chip Select Module SDRAM Control 8 SDCR CSORs SDRAM Timer SDTR DRAM Controller Outputs CS[7:0] ...
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Ethernet Module — 10 baseT capability, half- or full-duplex — 100 baseT capability, half duplex and limited throughput full-duplex (MCF5272) — On-chip transmit and receive FIFOs — Off-chip flexible buffer descriptor rings — Media-independent interface (MII) • Universal serial ...
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MCF5272 Architecture • System integration module (SIM) — System configuration including internal and external address mapping — System protection by hardware watchdog — Versatile programmable chip select signals with wait state generation logic — three 16-bit parallel input/output ...
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The Version 2 ColdFire core has a 32-bit address bus and a 32-bit data bus. The address bus allows direct addressing Gbytes. It supports misaligned data accesses and a bus arbitration unit for multiple bus masters. ...
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MCF5272 Architecture A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset to the MCF5272 not refreshed periodically by software. 1.2.2.4 Power Management The sleep and stop power management modes ...
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Receive and transmit FIFOs minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided. Using a programmable prescaler or an external source, the MCF5272 system clock supports ...
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MCF5272-Specific Features for chip select 0 (CS0), which is active after power-on reset until programmed otherwise. BUSW1 and BUSW0 select the initial data bus width for CS0 only. A wake-up from sleep mode or a restart from stop mode does ...
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The QSPI has the following features: • Programmable queue to support transfers without user intervention • Supports transfer sizes bits in 1-bit increments • Four peripheral chip-select lines for control ...
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MCF5272-Specific Features 1-10 MCF5272 User’s Manual MOTOROLA ...
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Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5272. The chapter describes the V2 programming model implemented on the MCF5272. It also includes a full description of exception handling, data ...
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Features and Enhancements • Two-stage IFP (plus optional instruction buffer stage) — Instruction address generation (IAG) calculates the next prefetch address. — Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction bus. — Instruction buffer (IB) optional stage ...
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Operand Execution Pipeline (OEP) The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register file feeding an arithmetic/logic unit (ALU). For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and ...
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Features and Enhancements Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit.” • Signed and unsigned integer multiplies • Multiply-accumulate operations ...
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Data operand address breakpoint registers (ABHR/ABLR) — Data breakpoint register (DBR) • Data breakpoint mask register (DBMR) • Trigger definition register (TDR) can be programmed to generate a processor halt or initiate a debug interrupt exception. These registers can ...
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Programming Model Figure 2-3. ColdFire Programming Model 2.2.1 User Programming Model As Figure 2-3 shows, the user programming model consists of the following registers: • 16 general-purpose 32-bit registers, D0–D7 and A0–A7 • 32-bit program counter ...
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Stack Pointer (A7, SP) The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by ...
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Programming Model 2.2.1.6 MAC Programming Model Figure 2-3 shows the registers in the MAC portion of the user programming model. These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of ...
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System Byte Field T — Reset R/W R/W R R/W R/W Table 2-3 describes SR fields. Table 2-3. Status Field Descriptions Bits Name 15 T Trace enable. When T is set, the processor ...
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Integer Data Formats 2.2.2.4 Access Control Registers (ACR0–ACR1) The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions. Attributes include definition of cache mode, write protect and buffer write enables. See Section 4.5.3.2, “Access Control Registers (ACR0 and ...
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Organization of Integer Data Formats in Registers Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data registers, ...
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Addressing Mode Summary 2.4.2 Organization of Integer Data Formats in Memory All ColdFire processors use a big-endian addressing scheme. The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address longword data ...
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Table 2-5. ColdFire Effective Addressing Modes Addressing Modes Syntax Register direct Data Address Register indirect Address Address with (An)+ Postincrement –(An) Address with (d 16 Predecrement Address with Displacement Address register indirect with scaled index (d 8-bit displacement Xi*SF) Program ...
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Instruction Set Summary Table 2-6. Notational Conventions Instruction cc Logical condition (example: NE for not equal) An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example: ...
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Table 2-6. Notational Conventions (Continued) Instruction dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) + Arithmetic addition or postincrement indicator – ...
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Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction C Carry N Negative V Overflow X Extend Z Zero 2.6.1 Instruction Set Summary Table 2-7 lists implemented user-mode instructions by opcode. Table 2-7. User-Mode Instruction Set Summary Instruction Operand Syntax ...
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Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax CMPA <ea>y,Dx CMPI <ea>y,Dx DIVS <ea-1>y,Dx <ea>y,Dx DIVU <ea-1>y,Dx Dy,<ea>x EOR Dy,<ea>x EORI #<data>,Dx EXT #<data>,Dx EXTB Dx 1 HALT None JMP <ea-3>y JSR <ea-3>y LEA <ea-3>y,Ax LINK Ax,#<d16> LSL ...
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Instruction Set Summary Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax MOVEA <ea>y,Ax MOVEM #<list>,<ea-2>x <ea-2>y,#<list> MOVEQ #<data>,Dx MSAC Ry,RxSF MSACL Ry,RxSF,<ea-1>y,Rw MULS <ea>y,Dx MULU <ea>y,Dx NEG Dx NEGX Dx NOP none NOT Dx OR <ea>y,Dx Dy,<ea>x ORI ...
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Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax TRAPF None #<data> TST <ea>y UNLK Ax WDDATA <ea> default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode execution by setting ...
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Instruction Timing certain hardware resources within the processor are marked as busy for two clock cycles after the final DSOC cycle of the store instruction subsequent store instruction is encountered within this two-cycle window stalled until ...
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Table 2-10 lists execution times for MOVE.{B,W} instructions. Table 2-10. Move Byte and Word Execution Times Source Rx (Ax) Dy 1(0/0) 1(0/1) Ay 1(0/0) 1(0/1) (Ay) 3(1/0) 3(1/1) (Ay)+ 3(1/0) 3(1/1) -(Ay) 3(1/0) 31/1) (d16,Ay) 3(1/0) 3(1/1) (d8,Ay,Xi*SF) 4(1/0) 4(1/1) ...
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Instruction Timing MAC execution pipeline. In general, these store operations require only one cycle for execution, but if they are preceded immediately by a load, MAC, or MSAC instruction, the MAC pipeline depth is exposed and execution time is three ...
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Execution Timings—Two-Operand Instructions Table 2-14 shows standard timings for two-operand instructions. Table 2-14. Two-Operand Instruction Execution Times Opcode <ea> Rn add.l <ea>,Rx 1(0/0) add.l Dy,<ea> — addi.l #imm,Dx 1(0/0) addq.l #imm,<ea> 1(0/0) addx.l Dy,Dx 1(0/0) and.l <ea>,Rx 1(0/0) and.l ...
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Instruction Timing Table 2-14. Two-Operand Instruction Execution Times (Continued) Opcode <ea> Rn msac.l Ry,Rx 3(0/0) mac.w Ry,Rx,ea,Rw — mac.l Ry,Rx,ea,Rw — moveq #imm,Dx — msac.w Ry,Rx,ea,Rw — msac.l Ry,Rx,ea,Rw — muls.w <ea>,Dx 4(0/0) mulu.w <ea>,Dx 4(0/0) muls.l <ea>,Dx 6(0/0) mulu.l ...
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Table 2-15. Miscellaneous Instruction Execution Times (Continued) Opcode <ea> movem.l <ea>,&list — movem.l &list,<ea> — nop 3(0/0) pea <ea> — pulse 1(0/0) stop #imm — trap #imm — trapf 1(0/0) trapf.w 1(0/0) trapf.l 1(0/0) unlk Ax 2(1/0) wddata.l ...
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Exception Processing Overview Table 2-17. Bcc Instruction Execution Times Opcode Forward Taken bcc 3(0/0) 2.8 Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 Family processors include the following: • A simplified exception ...
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When the index value is generated, the vector table contents determine the address of the first instruction of the desired handler. After the fetch of the first opcode of the handler is initiated, exception processing terminates and ...
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Exception Processing Overview 2.8.1 Exception Stack Frame Definition The exception stack frame is shown in Figure 2-10. The first longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword contains ...
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Vector number—This 8-bit field, vector[7–0], defines the exception type calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-18. 2.8.2 Processor Exceptions Table 2-21 describes MCF5272 exceptions. Table 2-21. ...
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Exception Processing Overview Table 2-21. MCF5 Exception Trace ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode Exception (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only ...
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Table 2-21. MCF5 Exception Interrupt Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized Exception and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. Reset Asserting the reset input signal (RSTI) ...
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Exception Processing Overview 2-32 MCF5272 User’s Manual MOTOROLA ...
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Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5272 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.1 Overview The MAC unit provides hardware ...
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Overview Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application ...
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These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. • Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands ...
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Overview The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for filling registers quickly ...
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Data Representation The MAC unit supports three basic operand types: • Two’s complement signed integer: In this format, an N-bit operand represents a number within the range -2 of the least significant bit. • Two’s complement unsigned integer: In ...
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MAC Instruction Execution Timings 3-6 MCF5272 User’s Manual MOTOROLA ...
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Chapter 4 Local Memory This chapter describes the MCF5272 implementation of the ColdFire Version 2 core local memory specification. It consists of the following sections. • Section 4.3, “SRAM Overview,” and Section 4.4, “ROM Overview,” describe the on-chip static RAM ...
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Local Memory Registers 4.2 Local Memory Registers Table 4-1 lists the local memory registers. Note the following: • Addresses not assigned to the register and undefined register bits are reserved. Write accesses to these bits have no effect; read accesses ...
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SRAM Base Address Register (RAMBAR) RAMBAR determines the base address location of the internal SRAM module, as well as the definition of the types of accesses allowed for it. • RAMBAR is a 32-bit write-only supervisor control register. It ...
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SRAM Overview Table 4-2. RAMBAR Field Description (Continued) Bits Name 5–1 C/I, Address space masks (ASn). These fields allow certain types of accesses to be masked, or SC, inhibited from accessing the SRAM module. These bits are useful for power ...
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Programming RAMBAR for Power Management Depending on the configuration defined by RAMBAR, instruction fetch accesses can be sent to the SRAM module, ROM module, and instruction cache simultaneously. If the access is mapped to the SRAM module, it sources ...
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ROM Overview 4.4.2 ROM Programming Model The MCF5272 implements the ROM base address register (ROMBAR), shown in Figure 4-2 and described in the following section. 4.4.2.1 ROM Base Address Register (ROMBAR) ROMBAR determines the base address location of the internal ...
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Programming ROMBAR for Power Management Depending on the ROMBAR configuration, memory accesses can be sent to the ROM module and the cache simultaneously access hits both, the ROM module sources read data and the instruction cache access ...
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Instruction Cache Overview The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded into the instruction cache. The instruction cache also contains a 16-byte fill buffer that provides temporary storage for the ...
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Instruction Cache Operation The instruction cache is physically connected to the ColdFire core's local bus, allowing it to service all instruction fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's ...
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Instruction Cache Overview if (address == ACR0-address including mask) effective attributes = ACR0 attributes else if (address == ACR1-address including mask) effective attributes = ACR1 attributes else effective attributes = CACR default attributes Addresses matching an ACR can also be ...
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The cache-inhibited fill-buffer bit, CACR[CEIB], is set. • The access is an instruction read. • The access is normal (that is 0). In this case, a fetched line is stored in the fill buffer and remains valid ...
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Instruction Cache Overview When an external fetch is initiated and data is loaded into the line-fill buffer, the instruction cache maintains a special most-recently-used indicator that tracks the contents of the fill buffer versus its corresponding cache location. At the ...
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The reset value column indicates the initial value of the register at reset. Uninitialized fields may contain random values after reset. • The access column indicates whether the corresponding register can be read, written or both. Attempts to read ...
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Instruction Cache Overview Table 4-8. CACR Field Descriptions (Continued) Bits Name 27 CFRZ Cache freeze. Allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can be initiated and loaded into the line-fill buffer, ...
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Table 4-8. CACR Field Descriptions (Continued) Bits Name 1–0 CLNF Control longword fetch. Controls the size of the memory request the cache issues to the bus controller for different initial line access offsets. CLNF 4.5.3.2 Access Control ...
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Instruction Cache Overview Table 4-9. ACRn Field Descriptions (Continued) Bits Name 14–13 SM Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address range or if the type of access is a don’t care. 00 Match ...
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Chapter 5 Debug Support This chapter describes the Revision A enhanced hardware debug support in the MCF5272. 5.1 Overview The debug module is shown in Figure 5-1. Control PST[3:0], DDATA[3:0] BKPT Figure 5-1. Processor/Debug Module Interface Debug support is divided ...
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Signal Description 5.2 Signal Description Table 5-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in Section 5.8, “Motorola-Recommended ...
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External development systems can use PST outputs with an external image of the program to completely track the dynamic execution path. This tracking is complicated by any change in flow, especially ...
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Real-Time Trace Support Table 5-2. Processor Status Encoding (Continued) PST[3:0] Hex Binary 0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle ...
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PSTCLK PST 0x5 DDATA 0x0 Figure 5-3. Example JMP Instruction Output on PST/DDATA PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the subsequent 4 nibbles of DDATA display the lower 2 ...
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Programming Model Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care). All debug control registers are writable from the ...
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Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. CSR is write-only from the programming model. It can be read or written through the BDM port using the commands. WDMREG 5.4.1 ...
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Programming Model Table 5-5. AATR Field Descriptions Bits Name 15 RM Read/write mask. Setting RM masks R in address comparisons. 14–13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons. 12–11 TTM Transfer type ...
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Field Reset R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the ABLR is accessible in supervisor mode as debug control register 0x0D using ...
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Programming Model 31 28 Field BSTAT Reset 0000 1 R Field MAP TRC EMU DDC Reset R/W R/W R/W R/W R/W DRc[4–0] 1 Bit 7 is reserved for Motorola use and ...
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Table 5-8. CSR Field Descriptions (Continued) Bit Name 13 EMU Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See Section 5.6.1.1, “Emulator Mode.” 12–11 DDC Debug data control. Controls operand data capture for DDATA, ...
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Programming Model 31 Field Reset R/W DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction and through the BDM port using the DBMR is accessible in supervisor mode as debug control register 0x0F,using the ...
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TDR is configured appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are compared with the processor’s program counter register, as defined in TDR. Figure 5-9 shows the PC breakpoint register. 31 Field Reset R/W Write. PC ...
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Programming Model The debug module has no hardware interlocks prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13])before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. ...
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Table 5-14. TDR Field Descriptions (Continued) Bits Name 21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value ...
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Background Debug Mode (BDM) 4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution ...
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PSTCLK DSCLK DSI BDM State Current State Machine DSO Figure 5-12. BDM Serial Interface Timing DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as ...
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Background Debug Mode (BDM) Table 5-15. Receive BDM Packet Field Description Bits Name 16 S Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug ...
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Table 5-17. BDM Command Summary Command Mnemonic Read A/D / Read the selected address or data register and RAREG register return the results through the serial interface. RDREG Write A/D / Write the data operand to the specified address or ...
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Background Debug Mode (BDM) 15 Operation Figure 5-15. BDM Command Format Table 5-18 describes BDM fields. Table 5-18. BDM Field Descriptions Bit Name 15–10 Operation Specifies the command. These values are listed in Table 5-17 Reserved 8 R/W ...
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COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE READ (LONG) MS ADDR ??? "NOT READY" XXX "ILLEGAL" SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY DEBUG MODULE RESULTS FROM PREVIOUS COMMAND RESPONSES FROM THE DEBUG MODULE ...
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Background Debug Mode (BDM) • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the ...
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Write A/D Register ( The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: ...
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Background Debug Mode (BDM) Command/Result Formats: 15 Byte 0x1 Command Result X X Word Command 0x1 Result Longword Command 0x1 Result Figure 5-21. Command Sequence: READ (B/W) MS ADDR ??? "NOT READY" READ (LONG) MS ADDR ??? "NOT READY" Figure ...
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Write Memory Location ( Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses ...
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Background Debug Mode (BDM) Command Sequence: WRITE (B/W) MS ADDR ??? "NOT READY" WRITE (LONG) MS ADDR ??? "NOT READY" Figure 5-24. Operand Data This two-operand instruction requires a longword absolute address that specifies a location to which the data ...
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DUMP only when preceded by Otherwise, an illegal command response is returned. be used for intercommand padding without corrupting the address pointer. The size field is examined each ...
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Background Debug Mode (BDM) Command Sequence: DUMP (B/W) ??? DUMP (LONG) ??? Figure 5-26. Operand Data: None Result Data: Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word ...
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Command Formats: 15 Byte 0x1 Word 0x1 Longword 0x1 Figure 5-27. Command Sequence: FILL (LONG) FILL (B/W) MS DATA ??? "NOT READY" XXX "ILLEGAL" FILL (LONG) FILL (B/W) DATA ??? "NOT READY" XXX "ILLEGAL" Figure 5-28. Operand ...
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Background Debug Mode (BDM) 5.5.3.3.7 Resume Execution ( The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the ...
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Read Control Register ( Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a ...
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Background Debug Mode (BDM) 5.5.3.3.10 Write Control Register ( The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats Command 0x2 0x0 0x0 Result Figure 5-35. Command Sequence: ...
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Command/Result Formats Command 0x2 Result Figure 5-37. Table 5-20 shows the definition of DRc encoding. Table 5-20. Definition of DRc Encoding—Read DRc[4:0] Debug Register Definition 0x00 Configuration/Status 0x01–0x1F Reserved Command Sequence: RDMREG Figure 5-38. Operand Data: None Result ...
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Real-Time Debug Support Command Sequence: WDMREG ??? Figure 5-40. Operand Data: Longword data is written into the specified debug register. The data is supplied most-significant word first. Result Data: Command complete status (0xFFFF) is returned when register write is complete. ...
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The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also ...
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Real-Time Debug Support 5.6.1.1 Emulator Mode Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three different ways: • Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is ...
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Note that the debug module requires the use of the internal bus to perform BDM commands. In Revision A, if the processor is executing a tight loop that is contained within a single aligned longword, the processor may never grant ...
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Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax and.l Dy,<ea>x andi.l #imm,Dx asl.l {Dy,#imm},Dx asr.l {Dy,#imm},Dx bcc.{b,w} bchg #imm,<ea>x bchg Dy,<ea>x bclr #imm,<ea>x bclr Dy,<ea>x bra.{b,w} bset #imm,<ea>x bset Dy,<ea>x bsr.{b,w} btst #imm,<ea>x ...
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Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax mac.l mac.l Ry,Rx mac.l Ry,Rx,ea,Rw mac.w mac.w Ry,Rx mac.w Ry,Rx,ea,Rw move.b <ea>y,<ea>x move.l <ea>y,<ea>x move.l <ea>y,ACC move.l <ea>y,MACSR move.l <ea>y,MASK move.l ACC,Rx move.l MACSR,CCR move.l MACSR,Rx move.l MASK,Rx move.w ...
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Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax pea <ea>y pulse rems.l <ea>y,Dx:Dw remu.l <ea>y,Dx:Dw rts scc Dx sub.l <ea>y,Rx sub.l Dy,<ea>x subi.l #imm,Dx subq.l #imm,<ea>x subx.l Dy,Dx swap Dx trap #imm trapf ...
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The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated as instruction fetches. For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST ...
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Motorola-Recommended BDM Pinout 5.8 Motorola-Recommended BDM Pinout The ColdFire BDM connector, Figure 5-41 26-pin Berg connector arranged 2 x 13. Figure 5-41. Recommended BDM Connector 1 Developer reserved GND GND RESET 2 Pad-Voltage GND PST2 PST0 DDATA2 DDATA0 ...
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Chapter 6 System Integration Module (SIM) This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, power management, and system-protection functions for the MCF5272. 6.1 Features The SIM, shown in ...
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Features The following is a list of the key SIM features: • Module base address register (MBAR) — Base address location of all internal peripherals, SIM resources, and memory-mapped registers — Address space masking to internal peripherals and SIM resources ...
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Programming Model The following sections describe the registers incorporated into the SIM. 6.2.1 SIM Register Memory Map Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are memory-mapped registers offset from the ...
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Programming Model 6.2.2 Module Base Address Register (MBAR) The supervisor-level MBAR, Figure 6-2, specifies the base address and allowable access types for all internal peripherals written with a MOVEC instruction using the CPU address 0xC0F. (See the ColdFire ...
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Table 6-2. MBAR Field Descriptions Bits Field 31–16 BA Base address. Defines the base address for a 64-Kbyte address range 15–5 — Reserved, should be cleared Setting masks supervisor code space in MBAR address range 3 SD Setting ...
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Programming Model Table 6-3. SCR Field Descriptions (Continued) Bits Field 8 Priority Selects the bus arbiter priority scheme. 0 Ethernet has highest priority, DMA has next highest priority, CPU has lowest priority. 1 CPU has highest priority, DMA has next ...
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Table 6-4 describes SPR fields. Table 6-4. SPR Field Descriptions Bits Fields 15, 7 ADC, Address decode conflict. This bit is set when an address matches against two chip selects. If ADCEN ADCEN is also set, the bus cycle is ...
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Programming Model 31 30 Field BDMPDN Reset R Field DMAPDN PWMPDN QSPIPDN TIMERPDN GPIOPDN USBPDN UART1PDN UART0PDN Reset R/W 15 Field Reset R Field — Reset R/W Address Figure 6-5. Power Management Register (PMR) Table 6-5 ...
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Table 6-5. PMR Field Descriptions (Continued) Bits Field 21 QSPIPDN QSPI power-down enable. Controls the clocking to the QSPI module. 0 Clock enabled. 1 Clock disabled. 20 TIMERPDN Timer power-down enable. Controls the clocking to the timer module. 0 Clock ...
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Programming Model Table 6-5. PMR Field Descriptions (Continued) Bits Field 4 SLPEN Sleep enable. Allows the MCF5272 to be put into sleep mode in which internal clocking to the CPU is disabled.To enter sleep mode, the user must write to ...
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Sleep mode is exited by an interrupt request from by either an external device or an on-chip peripheral as detailed in Table 6-7. The sequence to enter stop mode is: 1. Set PMR[MOS]; clear PMR[SLPEN]. 2. Set the CPU interrupt ...
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Programming Model Field Version Design Center Number Value 0010 0100_01 forK75N R/W Address Figure 6-7. Device Identification Register (DIR) Table 6-8 describes the DIR fields. Table 6-8. DIR Field Descriptions Bits 31–28 Version number. Indicates the revision ...
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Watchdog Reset Reference Register (WRRR) The watchdog reset reference register (WRRR), Figure 6-8, contains the reference value for the software watchdog timeout causing a reset. 15 Field Reset R/W Address Figure 6-8. Watchdog Reset Reference Register (WRRR) Table 6-9 ...
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Programming Model 6.2.8.3 Watchdog Counter Register (WCR) The WCR, Figure 6-10, contains the 16 most significant bits of the software watchdog counter. Writing any value to WCR resets the counter and prescaler and should be executed on a regular basis ...
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Chapter 7 Interrupt Controller This chapter describes the operation of the interrupt controller portion of the system integration module (SIM). It includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. 7.1 Overview The ...
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Interrupt Controller Registers SYSTEM INTEGRATION MODULE (SIM) Figure 7-1. Interrupt Controller Block Diagram The SIM provides the following registers for managing interrupts: • Four interrupt control registers (ICR1–ICR4), which are used to assign interrupt levels to the interrupt sources. • ...
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Table 7-1. Interrupt Controller Registers (Continued) 0x030 0x034 Programmable interrupt transition register (PITR) [p. 7-7] 0x038 Programmable interrupt wakeup register (PIWR) [p. 7-8] 0x03C All external interrupt inputs are edge sensitive, with the active edge being programmable through PITR. An ...
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Interrupt Controller Registers Table 7-2. Interrupt and Power Management Register Mnemonics (Continued) Mnemonic or Portion Thereof ETx ERx ENTC QSPI IPL2, IPL1, IPL0 PI PDN WK SWTO 7.2.2 Interrupt Control Registers (ICR1–ICR4) ICR1–ICR4 are used to configure interrupts from various ...
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Table 7-3. ICR Field Descriptions Bits Name 31, 27, PI Pending interrupt. Writing a 1 enables the value for the corresponding IPL field to be set. Note: 23, 19, for external interrupts only, writing a one to this bit clears ...
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Interrupt Controller Registers Table 7-3 describes ICR3 fields. 7.2.2.4 Interrupt Control Register 4 (ICR4) ICR4, Figure 7-5, is used to configure interrupts from various on-chip sources Field QSPIPI QSPIIPL Reset 15 Field Reset R/W Addr Figure 7-5. ...
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Table 7-4 describes ISR fields. Table 7-4. ISR Field Descriptions Bits Field 31–4 — 0 Interrupt source is high. 1 Interrupt source is low. 3–0 — Reserved, should be cleared. 7.2.4 Programmable Interrupt Transition Register (PITR) The programmable interrupt transition ...
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Interrupt Controller Registers 31 30 Field INT1 INT2 Reset R Field UART1 UART2 Reset R Field USB4 USB5 Reset R Field QSPI INT5 Reset R/W Address Figure 7-8. Programmable Interrupt Wakeup Register (PIWR) Table ...
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If the core initiates an interrupt acknowledge cycle prior to the PIVR being programmed, the interrupt controller returns the uninitialized interrupt vector (0x0F). If the core initiates an interrupt acknowledge cycle after the PIVR has been initialized, but there is ...
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Interrupt Controller Registers Table 7-8. MCF5272 Interrupt Vector Table (Continued) Vector Number Bits 4–0 76 01100 77 01101 78 01110 79 01111 80 10000 81 10001 82 10010 83 10011 84 10100 85 10101 86 10110 87 10111 88 11000 ...
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Chapter 8 Chip Select Module This chapter describes the chip select module, including the chip select registers, the configuration and behavior of the chip select signals, and the global chip select functions. 8.1 Overview The chip select module provides user-programmable ...
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Chip Select Registers A detailed description of each bus access type supported by the MCF5272 device is given in Chapter 20, “w Bus Operation.” 8.1.3 Boot CS0 Operation CS0 is enabled after reset and is used to access boot ROM. ...
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Chip Select Base Registers (CSBR0–CSBR7) The CSBRs, Figure 8-1, provide a model internal bus cycle against which to match actual bus cycles to determine whether a specific chip select should assert. A bus cycle in a specific chip select ...
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Chip Select Registers Table 8-2. CSBRn Field Descriptions (Continued) Bits Name 4–2 TM Transfer modifier. Operates with TT to determine the access type 000 0x 001 0x 010 0x 011–100 0x 101 0x 110 0x 111 10 ...
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Table 8-4. Chip Select Memory Address Decoding Priority 8.2.2 Chip Select Option Registers (CSOR0–CSOR7) CSOR0–CSOR7, Figure 8-2, are used to configure the address mask, additional setup/hold, extended burst capability, wait states, and read/write access Field BAM Reset R/W ...
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Chip Select Registers Table 8-5. CSORn Field Descriptions (Continued) Name Name 9 RDAH Controls the address and attribute hold time after the termination, internal or external with TA read cycle that hits in the chip select address space. ...
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Chapter 9 SDRAM Controller This chapter describes configuration and operation of the synchronous DRAM controller component of the SIM including a general description of signals involved in SDRAM operations. It provides interface information for memory configurations using most common SDRAM ...
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SDRAM Controller Signals Figure 9-1 shows the SDRAM controller signal configuration. Internal 32-Bit Address Bus Figure 9-1. SDRAM Controller Signals Table 9-1 describes SDRAM controller signals. Table 9-1. SDRAM Controller Signal Descriptions Signal A10_PRECHG A10 precharge strobe. A precharge cycle ...
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Table 9-1. SDRAM Controller Signal Descriptions (Continued) Signal SDCLK SDRAM (bus) clock (same frequency as CPU clock). This dedicated output reduces setup and hold time uncertainty due to process and temperature variations. SDCLK is disabled for SDRAM power-down mode. SDCLKE ...
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Interface to SDRAM Devices Table 9-2 shows how BS[3:0] should be connected to DQMx for 16- and 32-bit SDRAM configurations. Table 9-2. Connecting BS[3:0] to DQMx 5272 16 Bit 32 Bit BS3 BS3 BS2 BS2 NC BS1 NC BS0 9.3 ...
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Table 9-5. Internal Address Multiplexing (16-Bit Data Bus) Device Pin SDRAM Pin A10 A9 A10_PRECHG A10/AP A12 A11 A13 A12 SDBA0 BA0 ...
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SDRAM Banks, Page Hits, and Page Misses 9.4 SDRAM Banks, Page Hits, and Page Misses SDRAMs can have up to four banks addressed by SDBA1 and SDBA0. The two uppermost address lines of the memory space are mapped to SDBA1 ...