NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 117

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

MOTOROLA
In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can
service additional read accesses from this buffer until another fill occurs or a
cache-invalidate-all operation occurs.
If ACRn[CM] indicates cache-inhibited, the controller bypasses the cache and performs an
external transfer. To ensure the consistency of cached data, execute a CPUSHL instruction
or set CACR[CINVA] to invalidate the entire cache before switching cache modes.
CPU space-register accesses, such as MOVEC, are treated as cache-inhibited.
4.5.2.4 Reset
A hardware reset clears the CACR disabling the instruction cache.
4.5.2.5 Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 4.5.1, “Instruction Cache Physical Organization,” the instruction
cache hardware includes a 16-byte line-fill buffer for providing temporary storage for the
last fetched instruction.
With the cache enabled as defined by CACR[CENB], a cacheable instruction fetch that
misses in both the tag memory and the line-fill buffer generates an external fetch. The size
of the external fetch is determined by the value contained in CACR[CLNF] and the miss
address. Table 4-8 shows the relationships between the CLNF bits, the miss address, and
the size of the external fetch.
Depending on the run-time characteristics of the application and the memory response
speed, overall performance may be increased by programming CLNF to values {00, 01}.
For all cases of a line-sized fetch, the critical longword defined by miss address bits 3–2 is
accessed first followed by the remaining three longwords that are accessed by incrementing
the longword address in 0-modulo-16 increments, as shown below:
if miss address[3:2] = 00
if miss address[3:2] = 01
if miss address[3:2] = 10
if miss address[3:2] = 11
• The cache-inhibited fill-buffer bit, CACR[CEIB], is set.
• The access is an instruction read.
• The access is normal (that is, TT = 0).
fetch sequence = {0x0, 0x4, 0x8, 0xC}
fetch sequence = {0x4, 0x8, 0xC, 0x0}
fetch sequence = {0x8, 0xC, 0x0, 0x4}
fetch sequence = {0xC, 0x0, 0x4, 0x0x8}
Tag array contents are not affected by reset. Accordingly,
system startup code must explicitly invalidate the cache by
setting CACR[CINVA] before the cache can be enabled.
Chapter 4. Local Memory
NOTE:
Instruction Cache Overview
4-11