NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 515

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

1
2
MOTOROLA
Figure 23-17 shows IDL master timings listed in Table 23-17.
Table 23-18 lists timing for IDL slave mode.
Name
P14
P20
P15a
P15b
P16a
P16b
P17a
P17b
P19a
P19b
DOUT1, DOUT3
DIN1, DIN3
P22
P23
P24
P25
P25
P26
P26
FSR occurs on average every 125 µs.
In IDL slave mode, DCL may be any frequency multiple of 8 KHz between 256 KHz and 4.096 MHz inclusive.
DFSC[3:1]
GDCL1_OUT
1
2
P2
FSR0, FSR1 period
FSR0 or FSC0 valid before the falling edge of DCL0 (setup time)
DCL clock frequency
DCL pulse width high
DCL pulse width low
FSR1 or FSC1 valid before the falling edge of DCL1 (setup time)
DCL0 to FSR0 or FSC0 input Invalid (hold time)
DCL1 to FSR1 or FSC1 input Invalid (hold time)
Delay from rising edge of DCL0 to low-z and valid data on DOUT0
Delay from rising edge of DCL1 to low-z and valid data on DOUT1 and
DOUT3
Delay from rising edge of DCL0 to high-z on DOUT0
Delay from rising edge of DCL1 to high-z on DOUT1 and DOUT3
Delay from rising edge of DCL1 to DFSC2, DFSC3 Invalid (output hold)
Data valid on DIN0 before falling edge of DCL0 (setup time)
Data valid on DIN1, DIN3 before falling edge of DCL1 (setup time)
Data valid on DIN0 after falling edge of DCL0 (hold time)
Data valid on DIN1, DIN3 after falling edge of DCL1 (hold time)
P7
Table 23-18. IDL Slave Mode Timing, PLIC Ports 0–3
P10
P3
Figure 23-17. IDL Master Timing
Chapter 23. Electrical Characteristics
Characteristic
P5
P11
PLIC Module: IDL and GCI Interface Timing Specifications
P1
P6
P4
P8
Min Typ
256
25
45
45
25
25
25
25
25
25
25
—
—
—
—
—
2
125
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P9
4096
Max
55
55
30
30
30
30
—
—
—
—
—
—
—
—
—
—
% of DCL period
% of DCL period
Unit
Khz
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µs
23-21