NNDK-MOD5272-KIT NetBurner Inc, NNDK-MOD5272-KIT Datasheet - Page 40

• Manufacturer Part Number: NNDK-MOD5272-KIT
• Description: KIT DEVELOP NETWORK FOR MOD5272
• Manufacturer: NetBurner Inc
• Series: ColdFire®r

Specifications of NNDK-MOD5272-KIT

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: MOD5272
• Primary Attributes: *
• Secondary Attributes: *
• Processor To Be Evaluated: MOD5272
• Interface Type: RS-232, RS-485, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 528-1001

Organization
xl
• Chapter 5, “Debug Support,” describes the Revision A hardware debug support in
• Chapter 6, “System Integration Module (SIM),” describes the SIM programming
• Chapter 7, “Interrupt Controller,” describes operation of the interrupt controller
• Chapter 8, “Chip Select Module,” describes the MCF5272 chip-select
• Chapter 9, “SDRAM Controller,” describes configuration and operation of the
• Chapter 10, “DMA Controller,” provides an overview of the MCF5272’s
• Chapter 11, “Ethernet Module,” describes the MCF5272 fast Ethernet media access
• Chapter 12, “Universal Serial Bus (USB),” provides an overview of the USB module
— Section 4.3, “SRAM Overview,” describes the MCF5272 on-chip static RAM
— Section 4.4, “ROM Overview,” describes the MCF5272 on-chip static ROM.
— Section 4.5, “Instruction Cache Overview,” describes the MCF5272 cache
the MCF5272.
model, bus arbitration, power management, and system-protection functions for the
MCF5272.
portion of the SIM. Includes descriptions of the registers in the interrupt controller
memory map and the interrupt priority scheme.
implementation, including the operation and programming model, which includes
the chip-select address, mask, and control registers.
synchronous DRAM controller component of the SIM, including a general
description of signals involved in SDRAM operations. It provides interface
information for memory configurations using most common SDRAM devices for
both 16- and 32-bit-wide data buses. The chapter concludes with signal timing
diagrams.
one-channel DMA controller intended for memory-to-memory block data transfers.
This chapter describes in detail its signals, registers, and operating modes.
controller (MAC). This chapter begins with a feature-set overview, a functional
block diagram, and transceiver connection information for both MII and seven-wire
serial interfaces. The chapter concludes with detailed descriptions of operation and
the programming model.
of the MCF5272, including detailed operation information and the USB
programming model. Connection examples and circuit board layout considerations
are also provided.
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples of how to minimize
power consumption when using the SRAM.
The ROM module contains tabular data that the ColdFire core can access in a
single cycle.
implementation, including organization, configuration, and coherency. It
describes cache operations and how the cache interacts with other memory
structures.
MCF5272 User’s Manual
MOTOROLA